Advanced Micro Devices Corporation

National Semiconductor Corporation

Sun Microsystems, Inc.

Oracle America, Inc.

Other

Dennis L Wendell

John Christian Holst

Jun Liu

Yolin Lih

Ajay Bhatia

Daniel Fung

Shyam Sundar Balasubramanian

Pradeep Kaushik

Benjamin S Wong

John Gregory Favor

Hamid Partovi

Amos Ben-Meir

Donald A Draper

Howard L Levy

Jin-uk Shin

Terry L Lyon

Yi-Ren Warry Hwang

James E Demaris

Suresh Seshadri

Jeffrey B Chritz

Charles Hochstedler

Dan Lunecki

Effendy Kumala

Imtiaz P Shaik

A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

Memory device with split power switch

An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin can be more conveniently controlled.

Elastic power for read margin

A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block further propagation of the logic value of the input signal from the first stage circuit to the second stage circuit.

NAND/NOR registers

An elastic power header device and methods of operation are provided to improve both the read and the write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin, write margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin and the write margin can be more conveniently controlled.

Elastic power for read and write margins

An apparatus and method for controlling and providing a robust, single entry cache memory is described in connection with an on-board cache memory integrated with a microprocessor. By implementing the single entry cache memory in a redundancy array of the cache memory, CPU debug procedures may proceed independently of the cache debug by disabling part of the cache memory and enabling a dedicated single entry cache in the redundancy array. Use of a cache redundancy array for the single entry cache imposes no area or latency penalties because the existing cache redundancy array already matches the latency of the cache.

Method and apparatus for using a fault tolerant memory in processor testing and design

An apparatus and method for controlling and providing off-pitch shifting circuitry for implementing column redundancy in a multiple-array memory is described in connection with an on-board cache memory integrated with a microprocessor. Depending upon the particular sub-array being accessed, shift position data is provided to a shared, off-pitch shift circuit to control the read and/or write operations for the memory. A register bank stores data identifying the defective columns which is compared to the incoming address information to detect any matches. In response to a match, control information is provided to the off-pitch shift circuit for shifting or re-routing the incoming data to a non-defective address in the memory. In this way, defective columns located in different positions in each sub-array can be replaced by redundant paths, thereby repairing the cache and increasing the manufacturing yield of microprocessors with an on-board cache memory.

Off-pitch column redundancy using dynamic shifters

A Negative Bias Temperature Instability (NBTI) tolerant sense amplifier is provided. The sense amplifier includes an input stage having a pair of balanced isolation devices. Each of the balanced isolation devices has an input connected to receive a separate one of a pair of differential input signals. Each of the balanced isolation devices also has a gate that is connected to receive a common bias voltage. The sense amplifier further includes a sense stage connected to the input stage. The sense stage is configured to receive and amplify a higher signal to be provided by the pair of balanced isolation devices. The sense amplifier is also equipped to operate a low voltage levels.

Sense amplifier and method for making the same

A memory system using low impedance memory bitlines that eliminate the need for a precharge clock signal. An equilibration circuit controlled by a reference voltage is connected to the first and second bitlines of a memory cell and is operable to maintain a predetermined equilibrium condition between the first and second bit lines. The equilibration circuit is operable to generate an impedance load in the first and second bit lines at a level that allows generation of differential signals in the bit lines. The memory cell bitlines can move from a sensed state 'low' to the opposite state 'high' without an intervening precharge, thereby providing a significant increase in performance.

Low impedance memory bitline eliminating precharge

In a circuit that generates a plurality of dynamic signals in a self-resetting signal path, none of which may occur in some cycles, a handshake circuit generates a signal indicative of whether none of the signals occurred and incorporates the plurality of dynamic signals and the signal indicative that none of the signals occurred into a handshake signal. The handshake circuit generates a 'normal operation' signal designating that one of the plurality of dynamic signals occurred. The handshake circuit also generates a 'reset' signal indicative that none of the signals occurred.

Handshake circuit and operating method for self-resetting circuits

A regenerative amplifier is coupled to a combinational current-steering network to provide a combinational logic and register combination. A differential change in current on the register's input nodes due to current steering is amplified to provide complementary logic values at the output nodes of the register responsive to a clock signal. Various combinational logic functions are implemented by current steering networks. Such a configuration provides the advantages of economy of size, cost and power consumption in the combinational layout because the current steering transistors may be made smaller. Furthermore, such a configuration provides the advantage of decreased set-up time in a registered data path and immunity from external sources of noise via common mode rejection. In one embodiment, a regenerative amplifier includes cross-coupled inverters. Current steering circuits steer current between regenerative amplifier input nodes depending on the output value of the logical function implemented by the combinational network.

Register with current-steering input network

A current-sensing static amplifier-based flip-flop is useful for high-performance VLSI circuitry. The flip-flop has a short latency and a small hold time, advantageous features in high-performance microprocessors. A flip-flop circuit includes an amplifier stage and a static stage. The amplifier stage has a data input terminal and a clock input terminal. The amplifier stage includes a dual-output amplifier having two output lines connected respectively to two current pulldown paths and a gate connected between the current pulldown paths. The static stage is connected to the amplifier stage and including a static latch.

Amplifier-based flip-flop elements

A power-up initialization circuit includes a transistor that generates a positive leakage current at the onset of a power-up ramp voltage. The positive leakage current drives a first node connected to a latch to a first defined state. The latch drives a complementary second node to a second defined state, complementary to the state of the first node. The latch acts as a keeper that is switchable and allows current flow during power-up but prevents leakage current when the power-up is complete and nodes are set to selected states. A keeper is a circuit element that holds a dynamic circuit to a static behavior. One type of keeper is a latch. Another type of keeper is a MOSFET transistor having a thin channel width and a gate terminal connected to a reference such as a ground or VSS reference. A power-up initialization circuit includes a capacitive switch connected to a power source and connected to a power-up control node, and a current source connected to the power source and connected to an internal node. The current source has a control terminal connected to the power-up control node. The current source sets a state at the internal node according to a signal on the power-up control node. The power-up initialization circuit furthers includes a latch connected to the internal node and connected to a controlled node. The latch sets a state of the controlled node opposite the state of the internal node.

Power-up initialization circuit that operates robustly over a wide range

CMOS logic is coupled to dynamic logic which in turn is coupled to CMOS logic such than a clock is not required for the dynamic logic. Such a mixed static/dynamic buffer provides increased speed and fan-out. A buffer includes a dynamic circuit block coupled between static input and output blocks. The dynamic circuit block receives static true and complement input signals and provides dynamic output control signals responsive thereto. The dynamic circuit block dynamically changes the dynamic output control signals responsive to detecting a transition of the true input signal. The dynamic circuit block does not receive a clock signal. The static output block receives the dynamic output control signals and provides a static output signal responsive thereto. The static input block receives the true input signal and precharges the dynamic circuit block after the dynamic circuit block dynamically changes the dynamic output control signals.

Buffer for static in/static out dynamic speed

A scannable sense amplifier is provided in which the transfer circuits are implemented using only a pair of NMOS transistors added to column pitched circuits between adjacent sense amplifiers.

Efficient on-pitch scannable sense amplifier

A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.

Growing community of inventors

Pleasanton, CA, United States of America

Dennis L Wendell