Mostek Corporation

Benchmarq Microelectronics, Inc.

Dennis L Segers

Robert J Proebsting

Andrew C Graham

A central processing unit (10) has a cache memory system (24) associated therewith for interfacing with a main memory system (23). The cache memory system (24) includes a primary cache (26) comprised of SRAMS and a secondary cache (28) comprised of DRAM. The primary cache (26) has a faster access than the secondary cache (28). When it is determined that the requested data is stored in the primary cache (26) it is transferred immediately to the central processing unit (10). When it is determined that the data resides only in the secondary cache (28), the data is accessed therefrom and routed to the central processing unit (10) and simultaneously stored in the primary cache (26). If a hit occurs in the primary cache (26), it is accessed and output to a local data bus (32). If only the secondary cache (28) indicates a hit, data is accessed from the appropriate one of the arrays (80)-(86) and transferred through the primary cache ( 26) via transfer circuits (96), (98), (100) and (102) to the data bus (32). Simultaneously therewith, the data is stored in an appropriate one of the arrays (88)-(94). When a hit does not occur in either the secondary cache (28) or the primary cache (26), data is retrieved from the main system memory (23) through a buffer/multiplexer circuit on one side of the secondary cache (28) and passed through both the secondary cache (28) and the primary cache (26) and stored therein in a single operation due to the line for line transfer provided by the transfer circuits (96)-(102).

Integrated cache memory system with primary and secondary cache memories

A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit to determine the implementation of redundant elements in a semiconductor memory. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit. The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory. An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array. After the memory array has previously received a first data state and the circuit (62) is activated to apply a second data state to the redundant column (63) the memory array is read and each column which produces a second data state is determined to be a redundant column. With knowledge of the column substitution algorithm, it can then be determined which of the redundant columns have been programmed to replace specific original columns. This method can therefore determine the physical configuration of the memory circuit despite the incorporation of redundant elements into the primary memory array.

Testing and evaluation of a semiconductor memory containing redundant

A dynamic RAM integrated circuit has improved resistance to soft errors caused by alpha particles by changing the trip-point voltage of the sense amplifier from a first value that provides resistance to bit line errors to a second, lower value that provides resistance to cell errors.

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Lewisville, TX, United States of America

Dennis L Segers