International Business Machines Corporation

Dennis L Moeller

Patrick M Bland

Richard Gerard Hofmann

Lance M Venarchick

Richard Alan Dayan

John W Blackledge, Jr

Palmer E Newman

Daniel P Fuoco

Jonathan H Raymond

Daniel R Cronin, Iii

Suksoon Yong

Luis A Hernandez

Esmaeil Tashakori

Eric Mathisen

Kenneth J Zubay

Mark Edward Dean

Sagi Katz

Yuan-Chang Lo

Peter Juergen Klim

Moises Cases

Richard Bealkowski

Stephen Douglas Weitzel

David Lee Randall

Duy Q Huynh

Robert G Baker

William Alan Wall

Matthew T Mittelstedt

Grant L Clarke, Jr

Loc Tien Tran

Amy Louise Kulik

Paul R Swingle

Dhruvkumar M Desai

JoAnna B Yoder

Kimthanh D Le

Michael J DeLoye

John Joseph Szarek

Robert B Haig

Patrick E McCourt

Avery M Lyford

Essy Tashakori

This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. The present invention protects a trusted personal computer system against a probing attack, in which an unauthorized user would attempt to overcome the security feature elements of the personal computer system by inserting some form of probe into an opening provided in the system enclosure for other, legitimate, purposes such as cooling air flow or removable media insertion. A plurality of security feature elements are mounted within the enclosure for selective activation to secure and non-secure states and are disposed at locations inaccessible to any unauthorized user of the personal computer system attempting to affect the operation of any one of the security feature elements by insertion of a probe through an opening.

Trusted personal computer system with limited accessibility

A method and arrangement is provided to support both fast Programmed Input/Output (PIO) and third party Direct Memory Access (DMA) data transfers between a system memory and Integrated Drive Electronics (IDE) drives. A DMA controller attached to an ISA bus supplies address, read and write signals in third party DMA data transfers. An IDE controller provides control signals to support the DMA data transfers. The IDE controller additionally provides address and control signals to support the PIO data transfers at local bus speeds. A local bus-ISA bridge is incorporated to support the system memory that resides on the local bus. An arbitration circuit arbitrates access to the ISA bus, and allows the IDE controller to seize the ISA bus for fast PIO data transfer.

Local bus-ISA bridge for supporting PIO and third party DMA data

A computer system having a peripheral bus and a digital signal processor (DSP) local bus interfacing to the peripheral bus via an extended bus interface circuit (EBIC). The DSP local bus is configured such that devices, which are typically two or more DSPs, electrically connected to the DSP local bus may transfer data to other devices connected to the DSP local bus regardless of data transfer activity of the peripheral bus. Moreover, as seen from the peripheral bus, the devices connected to the DSP local bus have the same arbitration level. However, as seen from the DSP local bus, each device connected to the DSP local bus has a unique arbitration level determined by the priority of the tasks executing on the respective devices, as determined by a DSP operating system.

Computer system having a DSP local bus

A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer. The DMA has registers for storing base addresses and registers for storing current addresses. The base addresses and the current addresses indicate destinations of transfer data in the DMA transfer. A power management device is coupled to the DMA control circuit and has logic for causing the computer system to enter a suspend mode. A base address register read circuit is coupled to the base address registers. Prior to entering the suspend mode, the base address register read circuit provides one of the base addresses to be read by a central processing unit (CPU) onto disk storage. When the power management device resumes operation of the computer system, the base address that has been read is written back to reprogram the DMA control circuit. The ability to read the base address registers and store base addresses allows a reduction or elimination of shadow registers that shadow every write to a base address register.

Bridge between two buses of a computer system with a direct memory

This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

Personal computer with processor reset control

A system having an industry standard architecture (ISA) bus with a 24-bit memory addressing capacity and a peripheral controller interconnect (PCI) bus with a 32-bit memory addressing capacity, is provided with a bridge coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) controller circuit that generates 32-bit memory addresses for DMA transfer operations over the PCI bus. The DMA controller circuit includes a pair of cascaded DMA controllers that generate the 16 least significant bits of the 32-bit memory addresses, and address extension logic having a low page register that provides the 8 next most significant bits of the 32-bit memory addresses, and a high page register that provides the 8 most significant bits of the 32-bit memory addresses. The 16 bits provided by the low and high page registers are concatenated with the lower 16 bits to form the 32-bit addresses. The DMA controller circuit is also provided with count extension logic that increases the transfer count from a 16-bit number to a 24-bit number, so that larger segments of memory may be moved in the individual DMA transfers.

A bridge interface for buses in a computer system has a direct memory access (DMA) controller that controls memory transfers in the computer system. The DMA controller has a pair of cascaded DMA controller chips that provide a plurality of DMA channels. A multiplexer circuit receives memory address signals from the DMA controller chips. The memory address signals are received in both a shifted form and an unshifted form at the multiplexer inputs. By selection of the shifted or the unshifted memory address at the multiplexer, either even or odd addresses are produced at the multiplexer output for each DMA channel, thereby selectively providing 8-bit or 16-bit memory accesses. The control of the multiplexer is programmable for each DMA channel, providing dynamic configuration of the DHA channels as either 8-bit or 16-bit channels.

Bridge for interfacing buses in computer system with a direct memory

A bridge is provided between an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus and performs memory cycles on both buses simultaneously when a master on the ISA bus initiates a memory transfer. Data is steered between the ISA and PCI buses when a slave on the PCI bus claims the memory address within a predetermined time period after the memory cycle is initiated on the PCI bus. The ISA bus is isolated from the PCI bus when no slave on the PCI bus claims the memory address. This allows the memory cycle to be completed on the ISA bus, and the memory cycle on the PCI bus is terminated.

Bridge between two buses of a computer system that determines the

A bridge interface for a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer, and a scatter/gather unit coupled between the ISA bus and the DMA control circuit. The scatter/gather unit selectively provides the programming signals to the DMA control circuit directly or causes the programming signals to be provided over the ISA bus. Providing the programming signals to the DMA control circuit directly from the programming controller of the scatter/gather unit takes advantage of the location of both the DMA control circuit and the scatter/gather unit on the bridge chip. The program controller is able to program the DMA control circuit with I/O write cycles that take only one 33 MHz clock, instead of a plurality of 8 MHz clocks if the DMA control circuit is programmed with signals sent over the ISA bus. This provides an order of magnitude reduction is the time required to program the DMA control circuit.

Bridge interface between two buses of a computer system with a direct

This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

Personal computer with alternate system controller

A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. Devices coupled to the buses are either PCI bus-compliant devices or are non-PCI bus-compliant devices. A power management device in the computer system is able to place the computer system into a low power suspend mode, a resume mode and an active mode. The bridge has a multi-tiered arbitration device for arbitrating among the PCI bus-compliant devices and the non-PCI bus-compliant devices for control of the computer system. The arbitration device is responsive to the power management device to controllably suspend arbitration when the power management device indicates that the suspend mode is being entered.

Bridge for a power managed computer system with multiple buses and

In a personal computing system the function of the DMA controllers in the 'AT' or 'ISA' bus has been modified so that the system may select whether the 16-bit DMA channels are to be used as 8-bit DMA channels or 16-bit DMA channels. An 8/16-bit mode bit for each of the 16-bit DMA channels is written in a control register during the system Power On Self Test routine. Once the mode bit is written for each of the three 16-bit DMA channels, it may be read when the channel is active to select whether the channel is to operate as an 8-bit or 16-bit channel. With this mode bit information available, the page addressing may be selectively changed from 128k size pages to 64k size pages when a 16-bit DMA channel is to be converted to 8-bit. In addition, the byte addressing within a page may be changed from two byte addressing during 16-bit mode to single byte addressing during 8-bit mode.

Selectable 8/16 bit DMA channels for 'ISA' bus

This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. The features here described include a prioritized initial loading program for enabling initial loading of an operating system from a selected one of a plurality of sources, the prioritized initial loading program normally designating an interpreter program as a final option default in the event of failure of access to an operating system from any other one of the plurality of sources; a security utility program for enabling a designated user to (a) selectively modify the initial loading program by specifying the number and priority order of the plurality of sources and (b) selectively modify the initial loading program by deleting the interpreter program from the plurality of sources; a master cryptographic key for use in encrypting and decrypting data processed by the system CPU; and a second security utility program for enabling a designated user to modify the master cryptographic key.

Trusted personal computer system with management control over initial

This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. In particular, a personal computer system in accordance with this invention has a normally closed enclosure, at least one erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure and for invalidating any privileged access password stored in the erasable memory element in response to any switching of the tamper switch, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between the active and inactive states of the memory element and between entry and non-entry of any stored privileged access password. In the presently preferred form of the invention, two non-volatile erasable memory elements are provided, one an EEPROM and the other battery backed CMOS RAM.

Personal computer system with security features and method

This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of 'master' devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

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Boca Raton, FL, United States of America

Dennis L Moeller