John Fluke Mfg. Co., Inc.

Dennis L Lambert

Paul R Lantz

Alden J Carlson

Kasi S Bhaskar

Marshall H Scott

Alastair N Couper

A test system for functionally testing and troubleshooting microprocessor-based systems and assemblies is disclosed wherein the test system is connected in place of the microprocessor circuit of the unit being tested (UUT). The test system is itself a microprocessor-based system and includes a microprocessor circuit which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT. The test system periodically switches this microprocessor into signal communication with the UUT for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/O registers. In addition, a mode of operation is provided wherein the test system interrogates a fully functional assembly of the type to be tested to derive a memory map and test parameters that permit the test system to perform RAM, ROM, and I/O tests without prior knowledge of the UUT operational sequence or allocation of address space. A test probe provides a visual indication that the logic level at a monitored circuit node is high, low, invalid, or is a sequence of pulses of all three logic levels. The test probe also provides for injection of logical high pulses, logical low pulses or an alternating pulse sequence of high and low pulses. Probe logic level detection and pulse injection can be asynchronous or can be selectively synchronized so that logic level detection or pulse injection occurs with each UUT write or read operation.

Test apparatus for electronic assemblies employing a microprocessor

A converter that provides an analog (voltage) output signal that denotes either the period of an unknown low frequency signal or the ratio between the periods of two unknown low frequency signals is disclosed. The converter includes a ramp generator having a capacitor that is alternately charged in accordance with the periods of two low frequency signals. Between charging cycles the capacitor is discharged. When the period of an unknown low frequency signal is to be converted to analog form, one of the charge controlling signals is the unknown signal and the other signal is a known low frequency signal. When the ratio of the periods of two unknown low frequency signals is to be converted to analog form, the two unknown signals control the charging of the capacitor of the ramp generator. The ramp generator charge controlled by the period of the known signal (in the period conversion case) or one of the unknown signals (in the ratio conversion case) is used to control the level of a signal stored by a feedback sample and hold circuit, which circuit controls the output of the current source that charges the capacitor of the ramp generator. The ramp generator charge controlled by the other signal (the unknown in the period conversion case or the other unknown in the ratio conversion case) controls the level of an analog signal stored by an output sample and hold circuit, which signal represents: (a) the period of the unknown signal in the period conversion case; and, (b) the ratio between the periods of the unknown signals in the ratio conversion case.

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Bothell, WA, United States of America

Dennis L Lambert