Nvidia Corporation

Dennis K Ma

Marvin A Denman

Stephen David Glaser

Eric Tyson

Wei-Je Robert Huang

Mark Douglas Hummel

Samuel Hammond Duncan

Paolo Enrique Sabella

Lincoln G Garlick

Jonathan Owen

Michael Osborn

Jonah Matthew Alben

Denis J Foley

Praveen Jain

Oren Rubinstein

David William Nuechterlein

Atul Kalambur

David Brian Glasco

Sean Jeffrey Treichler

Brad W Simeral

Patrick Rene Marchand

David G Reed

Shane J Keil

Brian Kelleher

Richard A Silkebakken

Franck R Diard

Manas Mandal

Jeffrey M Smith

Michael Hopgood

Hitendra Dutt

Robert Huang

Shail Dave

Gary Ward

Peter Tong

Vishal Mehta

Sonny S Yeoh

Karan Gupta

Jeffrey J Irwin

Hungse Cha

Lei Tian

Prakash G Apte

Radha Kanekal

Samuel Vincent

Aron L Wong

Mark S Krueger

Richard B Kujoth

Devang Sachdev

Daphne Das

Vikramjeet Singh

Feroze Karim

Srikanth Devarapalli

A transmitter for a high speed serial communications link, a serial communications link, and a receiver for a high speed serial communications link are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium having multiple lanes, and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode, wherein in the safe mode at least one of the lanes is dedicated to transmitting a link detect signal for link detection.

Safe communication mode for a high speed link

A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

System and method for early packet header verification

A transmitter for a serial communications link, a serial communications link and an electronic system are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode.

A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect.

Technique for scaling the bandwidth of a processing element to match the bandwidth of an interconnect

A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.

System and method for enabling replay using a packetized link protocol

Techniques are disclosed for peer-to-peer data transfers where a source device receives a request to read data words from a target device. The source device creates a first and second read command for reading a first portion and a second portion of a plurality of data words from the target device, respectively. The source device transmits the first read command to the target device, and, before a first read operation associated with the first read command is complete, transmits the second read command to the target device. The first and second portions of the plurality of data words are stored in a first and second portion a buffer memory, respectively. Advantageously, an arbitrary number of multiple read operations may be in progress at a given time without using multiple peer-to-peer memory buffers. Performance for large data block transfers is improved without consuming peer-to-peer memory buffers needed by other peer GPUs.

Efficient CPU mailbox read access to GPU memory

A microprocessor within a processing unit is configured to manage to operation of a finite state machine (FSM) that, in turn, manages the operation of a data connector. The FSM may be a hardwired chip component that adheres to a communication protocol associated with the data connector. The microprocessor is configured to execute a software application in order to (i) apply configuration changes to the processing unit during state transitions initiated by the FSM and (ii) cause the FSM to initiate specific state transitions.

Managing state transitions of a data connector using a finite state machine

Non-contiguous or tiled payload data are efficiently transferred between peers over a fabric. Specifically, a client transfers a byte enable message to a peer device via a mailbox mechanism, where the byte enable message specifies which bytes of the payload data being transferred via the data packet are to be written to the frame buffer on the peer device and which bytes are not to be written. The client transfers the non-contiguous or tiled payload payload data to the peer device. Upon receiving the payload data, the peer device writes bytes from the payload data into the target frame buffer for only those bytes enabled via the byte enable message. One advantage of the present invention is that non-contiguous or tiled data are transferred over a fabric with improved efficiency.

Providing byte enables for peer-to-peer data transfer within a computing environment

A processing unit exchanges data with another processing unit across a data connector that supports a particular communication protocol. When the communication protocol is updated to support a new packet type, a specification of that new packet type may be stored within software registers included within the processing unit. Under circumstances that require the use of the new packet type, packet generation logic may read the packet specification of the new packet type, then generate and transmit a packet of the new type.

System and method for sending arbitrary packet types across a data connector

Methods and apparatus for providing additional storage, in the form of a hardware assisted stack, usable by software running an environment with limited resources. As an example, the hardware assisted stack may provide additional stack space to VBIOS code that is accessible within its limited allocated address space.

System and method for hardware assisted stack

A method comprises performing a first pass test over a plurality of sets of equalization coefficients to filter the plurality of sets of equalization coefficients to produce one or more filtered sets of equalization coefficients. Each filtered set of equalization coefficients meets a first predetermined threshold. The method also comprises performing a second pass test over the one or more filtered sets of equalization coefficients to determine a final set of equalization coefficients that meets a second predetermined threshold. The second pass test produces more accurate results than the first pass test.

Multipass approach for performing channel equalization training

Under some conditions, requests transmitted between different devices in a computing system may be blocked in a way that prevents the request from being processed, resulting in a deadlock condition. A skid buffer is used to allow additional requests to be queued in order to remove the blockage and end the deadlock condition. Once the deadlock condition is removed, the requests are processed and the additional buffer entries in the skid buffer are disabled.

Deadlock avoidance skid buffer

Methods, apparatuses, and systems are presented for performing asynchronous communications involving using an asynchronous interface to send signals between a source device and a plurality of client devices, the source device and the plurality of client devices being part of a processing unit capable of performing graphics operations, the source device being coupled to the plurality of client devices using the asynchronous interface, wherein the asynchronous interface includes at least one request signal, at least one address signal, at least one acknowledge signal, and at least one data signal, and wherein the asynchronous interface operates in accordance with at least one programmable timing characteristic associated with the source device.

Asynchronous interface for communicating between clock domains

Growing community of inventors

Austin, TX, United States of America

Dennis K Ma