International Business Machines Corporation

Dennis James Herrell

Frank F Fang

Arthur Davidson

A Josephson Self Gating And circuit which is powered by pulsed or clipped alternating current and provides true and complement outputs in response to true and complement inputs is disclosed. Inputs applied during the duration of the applied pulsed power or clipped alternating current are delivered to outputs which are maintained in that state in spite of a change of input within the given pulse duration. In one embodiment, the presence of an output signal interrupts a current path which, in turn, disables a pair of AND gates. These gates, even though the input to them changes, can provide no other output until the applied power falls to zero resetting the pair of AND gates which are latching in character. In another embodiment, current paths of one AND gate are cross-coupled with a current path of another AND gate. The interruption of current in a serially disposed Josephson device in one or the other of the current paths disables one or the other of the pair of AND gates preventing a change in outputs until the next cycle of applied pulsed or alternating current power. A latch circuit incorporating a pair of AND gates, a flip-flop and a Self Gating And circuit is also disclosed. The latch permits an input different from a previously applied input to the flip-flop to change the state of the flip-flop without changing the output of the Self Gating And during the application of a cycle of pulsed or alternating current power. The changed input to the flip-flop appears at the output of the Self Gating And circuit during the next cycle of applied pulsed or alternating current power.

Josephson self gating And circuit and latch circuit

An alternating current powering arrangement for use with Josephson junction devices which have bilateral gain characteristics is disclosed. Using an alternating current input to a Josephson junction logic circuit, it is possible to carry out a desired binary logic function during one half of an alternating current cycle; reset the logic circuit; and carry out a different binary logic function during the second half of the alternating current cycle. In the instance of latching circuits, the Josephson junction logic circuits are reset by the passage of the alternating current (which is normally the gate current of the Josephson junction) through zero every half cycle. In the instance of self-resetting devices, the Josephson junctions normally reset themselves to the zero voltage state. Single phase and multiphase logic circuit powering arrangements are shown including a shift register arrangement which requires only two phases to achieve passage of information from the input to the output of the shift register. All of the arrangements shown include regulating means formed from a string of series connected Josephson junctions, the I-V characteristic of which effectively clips both positive and negative portions of the applied alternating current. Also included is a scheme for powering the logic gates with a constant voltage source and the parallel arrangement thereof which provides stable and isolated logic circuits. Under such circumstances, the maximum value of current applied to the logic circuits is carefully controlled and a plurality of logic circuits may be connected in cascade but isolated from each other across the regulator string. The logic circuits utilized are per se well known and may consist of terminated line logic circuits connected to a pair of low impedance buses via a single current defining resistance or via a pair of current defining resistances of value equal to R/2, where the value of R is large relative to the characteristic impedance of the power buses. Also shown are transformer means for applying AC current from an AC source to a logic circuit via board-to-module, module-to-chip and chip-to-logic circuit transformers.

Josephson logic circuit powering arrangement

A Josephson junction terminated line logic powering scheme is disclosed wherein a logic gate and a regulating gate are utilized in at least a single logic circuit to provide a constant voltage to the logic circuit. The circuit comprises a terminated line logic gate with its associated sense gate and a regulating gate in series with the logic gate. When the logic gate is switched to the voltage state, it sends a disturb signal up and down the line which carries the gate current to the logic devices. A regulator gate which has already been biased to the voltage state is reset to the zero voltage state by the disturb signal. The resetting of the regulator gate sends out a disturb signal which cancels the original disturb signal with a small delay. The result of the combination of the disturbance generated by the logic gate and the regulating gate is an extremely narrow pulse with a maximum width equal to the round trip delay between the adjacent gates having an amplitude of I-I.sub.min. In the steady state, the total voltage drop across the supply line remains constant before and after logic operations. Thus, d.c. regulation problems are eliminated. Using the above approach for powering logic gates, it is possible to reset the logic gates by applying a control pulse to the regulating gates so that all of these gates which are in the zero voltage state will be switched to the voltage state. The disturbance resulting from this switching action resets the adjacent logic gate in the same manner as the logic gate disturbance resets the regulator gate. Regulating gates initially in the voltage state will not be affected by this operation.

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Somers, NY, United States of America

Dennis James Herrell