Infineon Technologies Ag

Dennis J Warner

Erdem Kaltalioglu

Mark Hoinkis

Matthias Hierlemann

Andy Cowley

Gerald R Friese

A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

Method and apparatus of stress relief in semiconductor structures

The present invention enables the quantification of line end shortening by utilizing a pattern of multiple conductive paths, each conductive path can include a conductor at each end, each conductor connected to a separate contact with the contacts connected by a polysilicon conductor. The conductors can vary in length by a constant increment from conductive path to conductive path, beginning with a length that results in a significant overlap at the contacts to a length that results in a significant underlap at the contacts. Resistance measurements of each conductive path can be made until a change either to or from an 'open' occurs; this is the point from which, using the constant increment, the LES can be characterized.

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Mechanicsville, VA, United States of America

Dennis J Warner