Microsoft Technology Licensing, LLC

Motorola Corporation

At&t Bell Laboratories

At+t Corp.

Dennis J Thompson

Murali Narayanan

Antonio Winslow Fernando

Tao Cao

Yong Zhong Wang

David Charles Huang

Fuyun Ling

Michael D Kotzin

Tyler A Brown

Stephen Lee Spear

Dennis R Schaeffer

John S Csapo

Tyler Alan Brown

Subhasis Laha

Aspects of the subject matter described herein relate to content sharing for mobile devices. In aspects, images that are created using mobile devices may be automatically uploaded to one or more targets. In addition, images created on the one or more targets may be automatically downloaded to the mobile device based on one or more criteria. A service facilitates transfer of images in both directions and includes a pluggable architecture in which forwarders for new targets may be added.

Content sharing for mobile devices

A wireless communication system (200, 300, 400, 500) mitigates the effects of excess timing delay caused by varying lengths of communication paths. In one general implementation, a transition communication path (206, 323, 329) is used to transfer a time-advanced version of a timing reference signal so that the cumulative time delay at a transition cell (209, 325, 331) is reduced. In another general implementation, the timing reference signal is time-advanced in all communication paths (403-411), and selected communication paths (403-407) include a time delay means (423-427, 503-507) such that the cumulative time delay at an area (421) near a target coverage area (130) is reduced. By reducing the cumulative time delay at the area (421) near the target coverage area (130), a handoff of a communication of a mobile station (128) into the target coverage area (130) can be performed.

Apparatus and method for mitigating excess time delay in a wireless

A receiver (156) includes both a coherent and noncoherent demodulator. When the confidence that estimates of the channel is high, the coherent demodulator is implemented. When the confidence that estimates of the channel is low, the noncoherent demodulator is implemented. A controlling microprocessor (162) controls the selection process and also provides a signal (158) to enable the noncoherent demodulator in instances when noncoherent demodulation would most likely be better than coherent demodulation. As an example, such an instance would be immediately after handoff of a mobile station (505) from a source base-station (503) to a target base-station (502).

Apparatus and method for demodulating a modulated signal

Bus arrangements are disclosed for interconnecting processors and main memory modules of a shared memory multiprocessor system. A single address bus interconnects all processors and memory modules, but odd and even memory modules communicate data to and from the processors via an odd and an even data bus. Each reading of memory occupies four bus cycles on one of the data buses. On the address bus, two of each of the four cycles are available for addressing odd and even memory modules, and the other two are available for sending invalidation addresses to the caches of the processors. The single address bus is used for transmitting a relatively narrow (32-bit) address word throughout the system, one address on each bus cycle, while the data buses are time shared to transmit a wide data word (256-bit) in four bus cycles, and each data bus is only connected to half of the main memory modules. Such an arrangement makes efficient use of limited bus resources to transmit information when and where it is needed.

Multiprocessor system using odd/even data buses with a timeshared

An address matcher and process for same used as an aid in debugging computer programs. Each of a plurality of random access memories (RAMs) is addressed by a different subfield of a computer memory address so that each access of the computer memory also causes a read of each of the RAMs. Each RAM is programmed with encoded data to define upper and lower block addresses for that subfield of the computer memory address with which it is associated. An output circuit decodes the encoded data read from each of the RAMs as a result of a computer memory access and generates a signal if the computer memory address lies within the monitored address block.

Computer memory address matcher and process

A synchronous apparatus synchronized to the operation of the slowest device is disclosed, comprising a plurality of devices such as first-in first-out buffer memories (FIFOs) connected to at least one synchronizing mechanism such as a full adder circuit. Each device generates a signal to indicating readiness to operate and a signal indicating completion of operation. Each device receives a signal causing the device to operate and a signal causing the device to stop operating. The synchronizing mechanism generates the operate signal upon sensing the readiness signals of all the devices and continues to generate the operate signal while at least one of the ready signals is sensed. The synchronizing mechanism generates the stop signal upon sensing the completion signal from all of the devices and continues to generate that signal while at least one of the completion signals is sensed.

Multi-device apparatus synchronized to the slowest device

Growing community of inventors

Geneva, IL, United States of America

Dennis J Thompson