Cadence Design Systems, Inc.

Dennis Huang

Ming Zhang

Ting Li

David Cooke Noice

Wei-Jin Dai

Jianmin Li

Stefanus Mantik

Hsi-Chuan Chen

Patrick John Eichenseer

Mitsuru Igusa

Anurag Tomar

Scot A Woodward

Shiu-Ping Chao

Adrian Aloysius Hendroff

Dewi Farrah Santoso

An approach includes a new power and ground structure description language (PSDL) will allow the user to describe the desired routing pattern for each layer and on a user defined region by region basis, including how the pattern will be laid out in the design with respect to other patterns from a different layer. The new PSDL also gives the complete picture of the entire power and ground structure, instead of just a layer-by-layer view from a single command. It also allowed flexibility in alignment especially when dealing with track misalignments, thus avoiding the extensive trial-and-error steps needed to calculate offsets and distances to maintain pattern alignment using previous approaches. Additionally, because PSDL is not tightly dependent on the design size and/or floorplan, transferring the desired power and ground structure from one design to another will be very easy with only few adjustments.

Pattern-based formal description language for describing a power/ground routing structure in an integrated circuit design

Disclosed is a method, system, and computer program product for automated implementation of pipeline flip-flops in an electronic design. Two operating modes can be used either together or separately to implement pipeline flip-flops. An analysis mode is employed to perform a determination of the number of stages of pipeline flip-flops needed for particular portions of an electronic design. A placement stage is used to place the pipeline flip-flops in the layout.

Method and system for implementing pipeline flip-flops

In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a 'master module' and the others designated 'clone modules'. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N&#x3e;0 iterations of the placement algorithm and/or after the placement algorithm has completed placement for the master module area.

Trial placement system with cloning

An integrated circuit (IC) layout process is organized into two phases. During the Phase of the process, a preliminary placement plan is generated fixing the position of every cell of an IC design described by a gate level netlist. A trial routing plan is also generated establishing approximate routes of the nets that are to interconnect cell terminals. The placement plan and the trial routing plan are then iteratively analyzed and modified as necessary to ensure that the layout meets various signal path timing, signal integrity, and power distribution and other constraints. Thereafter, at the start of Phase of the layout process, the trial routing plan is converted into a detailed routing plan specifying in detail the exact routes to be followed by all nets. The placement plan and detailed routing plan are then iteratively analyzed and modified as necessary to ensure that they meet all design constraints.

IC layout system having separate trial and detailed routing phases

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Palo Alto, CA, United States of America

Dennis Huang