Lsi Logic Corporation

Lsi Corporation

Ncr Corporation

Symbios Logic Inc.

Other

Avago Technologies General IP (singapore) Pte. Ltd.

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Maryland

Dennis E Gates

John R Kloeppner

Bret S Weber

Keith W Holt

Russell J Henry

Rodney A DeKoning

Mohamad H El-Batal

Rodney A Dekoning

Keith B DuLac

Robert E Stubbs

Scott E Greenfield

Charles D Binford

James D Thompson

Randolph Wesley Sterns

Charles E Nichols

Jeremy D Stover

Jason M Stuhlsatz

John W Stewart

Thomas L Langford, Ii

Curtis W Rink

Max L Johnson

Randy Kay Hall

Apparatus and circuitry are provided for supporting collection and/or verification of data integrity information. A circuitry in a storage controller is provided for creating and/or verifying a Data Integrity Block ('DIB'). The circuitry comprises a processor interface for coupling with the processor of the storage controller. The circuitry also comprises a memory interface for coupling with a cache memory of the storage controller. By reading a plurality of Data Integrity Fields ('DIFs') from the cache memory through the memory interface based on information received from the processor, the DIB is created in that each DIF in the DIB corresponds to a respective data block.

Apparatus and circuitry for memory-based collection and verification of data integrity information

Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.

Methods and apparatus for improved raid parity computation in a storage controller

A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.

Configurable storage array controller

Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.

Apparatus and methods for clustering multiple independent PCI express hierarchies

A method and system for facilitating communication between computer subnets are provided. One embodiment of the present invention comprises presetting buffers in an internal subnet, wherein the buffers help route external commands to a plurality of devices within the internal subnet. When a command from an external subnet is received by the internal subnet, the command is translated and sent to the proper internal device, as determined by the buffers. The command is then performed by the proper internal device. In another embodiment of the present invention, translation mapping are established for the internal subnet. When a command is received from an external subnet, the destination address associated with the command is translated to the address of the appropriate internal device, and the command is then sent directly to the internal device, which performs the command. By using either the buffer or translation mappings, the internal subnet appears to be a single device to the external subnet.

Infiniband isolation bridge merged with architecture of an infiniband translation bridge

Systems and methods for handling I/O requests from a host system to a storage system. A system includes an I/O module for processing I/O requests from a host system, a virtualized storage element, and a communication medium coupling the I/O module to the virtualized storage elements. The virtualized storage element includes a mapping table for translating virtual storage locations into physical storage locations and a plurality of physical storage locations. The virtualized storage element generates base virtual addresses using the mapping table to communicate the base virtual addresses to the I/O module. The I/O module generates specific virtual addresses using the base virtual addresses and using information derived from the I/O requests. The I/O module uses the specific virtual addresses in communication with the virtualized storage element to identify the physical storage locations in the virtualized storage element.

Method and apparatus for handling storage requests

A hardware assisted searching mechanism is provided that offloads the processor from searching operations. In a preferred embodiment, the hardware assisted searching mechanism performs a binary search of an associated 32 bit register against a binary search table that is set up by the firmware of the storage system. From this binary search table, an index into other structures stored in firmware is obtained that may be used to identify a target device. For example, when a search is to be performed due to receipt of an I/O operation, the firmware, i.e. software instructions stored in the persistent memory chip that are executed by the system processor, writes a 32 bit value to a hardware register that is used by the hardware assisted searching mechanism of the present invention. The hardware assisted searching mechanism performs a binary search of a binary search table based on the contents of the hardware register and returns an index of the entry in another hardware register. This index is then used to index into a storage device mapping structure stored in the firmware that are indexed in the same manner as the binary search table. The index provides a starting point in the storage device mapping structure and from this starting point, the logical unit number is used to identify a particular storage array and logical unit number for the destination of the I/O operation.

Method and apparatus for performing a high speed binary search in time critical environments

Methods and associated structure for improving storage system performance by reducing latency associated with communication medium transactions internal to a storage subsystem. In one aspect of the present invention, an I/O control element associated with a storage system transmits prefetch read requests to an associated storage element of the storage system in response to receipt of a host system request. This allows the storage element to commence data transfer to the I/O element in advance of the I/O element returning the data to the host system. Subsequent transfers of data from the storage element to the I/O element then overlap the transfer of data from the I/O element to the host. In another specific aspect of the present invention, methods and associated structures eliminate latency associated with PCI-X bus split transactions between the front-end (host interface portion) of the I/O element and the back-end (storage element interface) of the I/O element by overlapping the transfer of prefetched data to the host system with continued fetching of subsequent data from the storage element.

Method and structure for read prefetch in a storage complex architecture

A parity assist circuit that provides multiple XOR calculations using a scatter-gather list is disclosed. The parity assist circuit includes a control circuit that obtains a plurality of source operands in response to a scatter-gather list, and an XOR engine that provides a plurality of XOR products computed from the supplied source operands. Destination and length parameters in the scatter-gather list are used by the XOR engine to store the XOR computation product and to determine the length of the data in the source and destination blocks to be computed. Preferably, the parity assist circuit is part of a RAID controller that includes a processor and a cache memory. The parity assist circuit preferably utilizes the scatter-gather list to gather required source operands from a memory and to scatter multiple XOR products to the memory before sending an interrupt to the processor or receiving additional setup instructions from the processor, thereby providing rapid and efficient parity calculations and improving overall system performance of the RAID storage subsystem.

Disk array storage subsystem with parity assist circuit that uses scatter-gather list

A method of increasing computer system bandwidth for computer system having two or more memory complexes is disclosed in which exclusive OR operations are performed on the data from the data regions to generate parity information which is stored in the same single cache pool as the data regions. By using a single cache pool for related data regions, bandwidth and performance are improved.

Multiple memory system support through segment assignment

A shared resource manager circuit for use in conjunction with multiple processors to manage allocation and deallocation of a shared resource. The shared resource manager allocates and deallocates software resources for utilization by the processors in response to allocation and deallocation requests by the processors. The shared resource manager may include a bus arbitrator as required in a particular application for interfacing with a system bus coupled to the processors to provide mutual exclusion in access to the shared resource manager among the multiple processors. The shared resource manager may manage a memory block (FIFO queue) with multiple resource control blocks. A system may advantageously apply a plurality of shared resource managers coupled to a plurality of processors via a common interface bus. Each shared resource manager device may then be associated with management of one particular shared resource.

Shared resource manager for multiprocessor computer system

The present invention is directed to a system and method for eliminating race conditions in RAID controllers while utilizing a high bandwidth internal architecture for data flow. A remote memory controller of the present invention may ensure that an acknowledge signal is sent only after a memory operation has been actually completed. This may provide for remote direct memory access without coherency problems and data corruption problems while a high bandwidth data flow internal architecture is being utilized.

System and method to eliminate race conditions in input/output operations for high bandwidth architectures

Data transfers from the peripheral interface of a disk array to a data buffer are snooped to determine if the starting address of a data transfer matches an entry in a list of starting addresses for requested data. If a match is identified, third party transfer is initiated and the data is simultaneously transferred to the host interface of the host system. The resulting data bandwidth is increased. A throttling/suspension mechanism can temporarily or indefinitely hold up actual data movement into the data buffer to allow for temporary buffering and interface speed matching as data is transferred to the host interface.

Method of secondary to secondary data transfer with mirroring

The present invention provides storage system controllers and methods of controlling storage systems therewith. The controller ( ) includes a main processor ( ), a memory ( ), a device interface ( ) adapted to interface a peripheral component ( ), such as a RAID storage device, with the storage system controller, and an operations sequencer ( ). The main processor sequences a plurality of tasks to be executed to complete an operation. The operations sequencer coordinates an execution of the plurality of tasks. Methods of the invention include receiving a task status for each of the plurality of tasks that is executed, and issuing an interrupt to the main processor after all of the plurality of tasks of the operation are finished executing. In this manner, the operations sequencer offloads at least some of the main processor overhead to improve processor efficiency.

Methods and apparatus for raid hardware sequencing to achieve a higher performance raid architecture

In one embodiment, the present invention provides a storage system controller ( ) having a main processor ( ), a memory ( ) and a device interface ( ) adapted to interface with a peripheral component ( ). The controller further includes an interrupt management scoreboard ( ) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.

Growing community of inventors

Wichita, KS, United States of America

Dennis E Gates