Other

Tektronix, Inc.

Nexus Technology, Inc.

Dennis D Everson

Kenneth W Graham

Robert C Shelsky

Philip R Lantz

Christopher Shelsky

Stanley R Koslowski

An interposer comprising an array of top contacts on the top surface configured to interface with an integrated circuit package, a corresponding array of bottom contacts on the bottom surface configured to interface with a component beneath the interposer, through connections between corresponding top and bottom contacts and a plurality of signal probe points on the edge surface. The interposer may include an electrical pathway connecting a first through connection to a first signal probe point. The electrical pathway may contact the first through connection at a first intersection. A resistor may be disposed along the electrical pathway, between the first intersection and the first signal probe point. The electrical pathway from the first intersection to the resistor may be an unconditioned signal pathway. The electrical pathway from the resistor to the first signal contact may be a conditioned signal pathway. The unconditioned signal pathway may have a length of not greater than 0.20 inch.

Interposer with signal-conditioned edge probe points

A test assembly that may provide access to signals of a circuit that includes an integrated circuit. The test assembly may include structural members that limit movement of components relative to each other.

In-circuit test assembly

A bridge connector assembly may provide access to signals of a circuit that includes an integrated circuit. The bridge connector assembly may include first and second circuit boards that are mated edge to edge, structural members that maintain the position of each circuit board in relation to each other and connectors to carry signals from edge connectors on one board to corresponding connectors on the second board.

Board co-edge coupling with conductive elements

A circuit for software performance analysis implements a balanced binary tree in hardware. This circuit consists of a number of 'levels', each containing two (sets of) latches, a RAM, and a digital comparator. One of the latches, the data latch, is used to hold the data element being evaluated. The other latch, the results latch, stores partial results based on the comparisons performed on higher levels. The RAM is addressed by the contents of the results latch on the preceding level in combination with the output of the comparator on that same preceding level. The output of the RAM is compared by the digital comparator with the contents of the data latch, to produce an additional bit of results information for the next level. On each level, the RAM is preprogrammed with twice as many midpoint addresses as is the RAM on the preceding level. The outcome of the comparison done on any particular level is used, along with the results from preceding levels, as an address to access a RAM on the next level. Eventually, the last level is reached and there is only one range for each address generated on that level. This address is then applied to a count-holding RAM, and the contents of that RAM at that location is incremented to indicate that the incoming data element was within this data range.

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Banks, OR, United States of America

Dennis D Everson