International Business Machines Corporation

Dennis Charles Dubois

Claude Louis Bertin

Edmund Juris Sprogis

Wayne John Howell

Christopher P Miller

Kenneth E Beilstein, Jr

David J Perlman

Gustav Schrottke

Gordon Arthur Kelley

Jody John VanHorn

Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

Methods and apparatus for burn-in stressing and simultaneous testing of

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Salt Point, NY, United States of America

Dennis Charles Dubois