International Business Machines Corporation

Dennis C Reedy

Gene J Gaudenzi

Helmut Schettler

Nghia Van Phan

Allan Harvey Dansky

Herve L Beranger

John P Norsworthy

Chris J Rebeor

A receiver and level converter circuit is disclosed which may be used, for example, in converting low-level logic or other signals to high-level signals. In one embodiment, the circuit includes a differential amplifier having two feedback loops to provide an output signal having hysteresis, for increased gain, better noise margin and compensation. Each feedback loop includes a nonlinear difference network. In a preferred embodiment, the circuit is implemented in BICMOS technology, uses out-of-phase FETs as pull-down devices, and may be used to convert ECL-level signals to CMOS or BICMOS-level signals.

Receiver and level converter circuit with dual feedback

A small signal swing line driver, that generates a reduced amount of switching noise and also suppresses transients appearing on the line, is described. Specifically, the driver includes a clamp connected to the driver output to limit the maximum DC driver output level and to suppress voltage transients, e.g. reflections, spikes or the like, appearing on the driven line and caused by conditions external to the driver. The driver also contains circuitry to limit the transition times of the rising and falling edges of the driver output signal in order to reduce the amount of switching noise which is generated by the driver and thereafter coupled onto quiet lines.

Small signal swing driver circuit

The logic circuit disclosed exhibits push-pull output characteristic by employing a saturated feedback technique. This approach allows for emitter follower like up level drive and transient low impedance down level drive. The disclosed saturated feedback technique improves capacitive drive capability, reduces both load and circuit delay and reduces circuit power dissipation.

Switching circuit having low speed/power product

Power dissipation in an off-chip driver circuit is decreased by utilizing a selectively switched transistor to discharge the base of the output pull-down transistor, and by using a large resistance in the base current path for the first stage of the Darlington pull-up transistors. An additional transistor having a larger emitter area and coupled to a lower potential source is connected in parallel with the normal phase-splitter transistor to provide additional output current sinking capability, and a current mirror is connected to control the current through both the phase splitting transistor and the additional transistor to control the turn-on transition of the pull-down output transistor.

Low power off-chip driver circuit

Disclosed is a transistor-transistor-logic (TTL) circuit which is testable by D. C. Testing Techniques. The improvement includes a high impedance network for providing sufficient base drive to drive the output transistor into conduction when the malfunctioning input transistor fails to provide a turn-off logic level. The high impedance network can be a Schottky barrier diode and an epitaxial resistor connected in a series path between a potential supply and the base region of the output transistor.

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Stormville, NY, United States of America

Dennis C Reedy