Hewlett-packard Company

Intel Corporation

Dennis Brzezinski

Alan Hersh Karp

Rajat Agarwal

Peter Markstein

Rajiv Gupta

William S Worley, Jr

Frederic C Amerson

Clemens Roothaan

Scott Huddleston

A circuit and method for clipping input integers to a specified range comprising the steps of providing a mask wherein a bit is set for each out-of-range bit and not set for in-range bits and applying the mask to input integers so that any integers outside of the range is clipped to the quantity in the range closest to the integer, thereby producing output integers within a range specified by the mask. Other systems and methods are disclosed.

System and method for clipping integers

The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.

Vector memory operations

A floating point processing system which uses a multiplier unit and an adder unit to perform properly rounded quad precision floating point arithmetic operations using double-extended hardware. The floating point processing system includes quad data muxes for converting a quantity between a quad precision representation and a two double-extended precision quantities and vice versa, wherein the sum, if added at infinite precision, of the two double-extended precision quantities is equal to the quad precision quantity. The floating point processing system further include hardware for performing arithmetic operations on double-extended precision quantities.

Floating point arithmetic unit having logic for quad precision arithmetic

A multi-chip module includes a mechanically floated substrate on which integrated circuit devices are mounted. The substrate is located within a heat exchanger. In one embodiment, a spring or an array of springs biases the substrate upwardly to press the integrated circuit devices against a surface within the heat exchanger. The substrate is displaceable with respect to the heat exchanger, allowing accommodations to differences in thermal expansion coefficients and to non-uniformities resulting from less than exact manufacturing tolerances of the substrate, the heat exchanger and the integrated circuit devices. Another embodiment includes resting the substrate on a conformable membrane that is used to entrap a fixed volume of thermally-conductive liquid. The membrane-and-liquid arrangement mechanically floats the substrate and ensures a proper integrated circuit device/exchanger thermal interface. A flexible multi-conductor interconnect is electrically coupled to the substrate to allow conduction of signals to and from the substrate without interfering with the ability of the substrate to float mechanically. Also disclosed is a module in which the membrane-and-liquid arrangement is used at the integrated circuit device side of the substrate to achieve a deformable electrical and thermal flow path from the integrated circuit devices to the heat exchanger. The membrane adapts to variations in the heights and/or angles of the integrated circuit devices.

Mechanically floating multi-chip substrate

A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

Floating point arithmetic unit using modified Newton-Raphson technique

A multi-chip module having a conformal heat transfer interface to adapt to variations in the height and angle of integrated circuit chips and to achieve a thermal energy path between each chip and a heat sink. The conformal heat transfer interface includes a deformable metallic membrane and a liquid under pressure. The liquid has a high thermal conductivity and provides a pressure for deforming the metallic membrane to compensate for non-coplanarity of the chips. The module integrates the structural support, RF shielding, contamination-protection elements, and the heat-dissipating mechanism that are desired in the design of multi-chip modules. Double-sided cooling of the module significantly improves the thermal characteristics of a module, even in the absence of the conformal heat transfer interface.

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Sunnyvale, CA, United States of America

Dennis Brzezinski