Cisco Technology, Inc.

Dennis Briddell

William Robert Lee

Chirag Shroff

Martin Hughes

Harshad Bhaskar Nakil

Trevor Garner

John Kenneth Stacy

Trevor Gamer

Richard Kijewski

Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

Method and apparatus for synchronizing use of buffer descriptor entries for shared data packets in memory

A technique efficiently searches a hash table containing a plurality of 'ranges.' In contrast with previous implementations, the technique performs fewer searches to locate one or more ranges stored in the hash table. To that end, the hash table is constructed so each hash-table entry is associated with a different linked list, and each linked-list entry stores, inter alia, 'signature' information and at least one pair of values defining a range associated with the signature. The technique modifies the signature based on the results of one or more preliminary range checks. As a result, the signature's associated ranges are more evenly distributed among the hash table's linked lists. Thus, the linked lists are on average shorter in length, thereby enabling faster and more efficient range searches. According to an illustrative embodiment, the technique is applied to flow-based processing implemented in an intermediate network node, such as a router.

Header range check hash circuit

An information transport system includes a switching fabric that transfers information between network modules and between a host processor and the network modules. The switching fabric includes network module interfaces each associated with one or more network modules. The network module interfaces communicate with each other over a peer transaction bus to allow information to be transferred from one network module to another network module. The switching fabric also includes a processor interface associated with the host processor. The processor interface communicates with the network module interfaces over a host transaction bus to allow information transfer between the host processor and each network module. The peer transaction bus and the host transaction bus separately support routed packet data and peer to peer data transactions in order to prevent one type of transaction from blocking the other and avoid performance dependencies.

Switching fabric for interfacing a host processor and a plurality of network modules

A telecommunication environment includes an interface card and a system communication controller. The interface card provides an asynchronous transfer mode interworking capability that is compatible with a serial communications controller within the system communication controller. A transmission convergence sublayer within the interface card identifies valid asynchronous transfer mode cells carried over a T1/E1 trunk link. The valid asynchronous transfer mode cells are transferred to an encapsulation unit within the interface card. The encapsulation unit generates encapsulated frames in a protocol format understood by the serial communications controller. The encapsulated frames carry asynchronous transfer mode cells for processing by the system communication controller. A processor within the system communication controller performs segmentation and reassembly processes on payload extracted by the serial communications controller.

Device for interworking asynchronous transfer mode cells

A highly interleaved Time Division Multiplexing (TDM) format allows for high data density transfer for a given port at a communications controller. The port is coupled to a Time Slot Assigner (TSA) that will steer the provisioned timeslots of the interleaved TDM data to appropriate Serial Communication Controllers (SCCs), both which are internal to the communications controller. Entries in a Serial Interface Random Access Memory (SI RAM) that is coupled to the TSA and a lookup memory in a clock gapping function block located at a TDM interleaving circuit, are programmed by the communication controller to facilitate the TSA in steering the timeslots.

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Cary, NC, United States of America

Dennis Briddell