Agilent Technologies, Inc.

Dennis B Batchelor

David James Mielke

Systems and methods for pre-artwork timing verification of an integrated circuit design are provided. A representative system includes a computer and a memory element associated with the computer, the memory element configured to store information related to a contemplated integrated circuit design and model functional blocks of the integrated circuit responsive to the expected signal timing behavior of signals that traverse a functional block of interest. A representative method includes the following steps: acquiring circuit information that represents a plurality of functional blocks and a plurality of conductors of a contemplated integrated circuit, where the functional blocks are modeled by a plurality of signal characteristics; receiving timing constraints used in designing each respective functional block; generating a representation of each functional block; and applying the representation in a static timing analyzer.

System and methods for pre-artwork signal-timing verification of an integrated circuit design

A system and method for automating a static-timing analysis of an integrated circuit design are provided. A representative system includes a network coupled to a plurality of data storage devices, the data storage devices containing a knowledge base that defines an integrated circuit design; a computer coupled to the network, the computer including logic for receiving information defining an integrated circuit representation from the plurality of data storage devices; and a memory element associated with the computer, the memory element configured to store logic, the logic configured to generate static-timing scripts that reflect a plurality of timing models. A representative method includes the following steps: acquiring circuit information, the circuit information comprising a plurality of functional blocks; identifying a timing model to apply to each of the plurality of functional blocks; defining the hierarchical relationships between each of the plurality of functional blocks; extracting the circuit information responsive to the identifying and defining steps to complete a simulation of each of the plurality of functional blocks; and forwarding the simulation to a static-timing engine.

System and method for applying timing models in a static-timing analysis of a hierarchical integrated circuit design

Systems and methods for time-budgeting an integrated circuit design are provided. A representative system includes an information acquisition device, a computer, and a memory element associated with the computer, the memory element configured to store the information and associate a timing point that accounts for signal delays between the border of a functional block and the various circuits within the block. A representative method includes the following steps: acquiring circuit information that describes the conductors that traverse a border of the functional block, inserting a timing point in the information, determining a delay time in response to the timing point, and deriving a constraint in response to the delay time.

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Fort Collins, CO, United States of America

Dennis B Batchelor