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Rockwell International Corporation

Ford Microelectronics, Inc.

Dennis A Williams

David G McIntyre

Zachary J Lemnios

Chung-Lim Lau

Frank J Ryan

Richard P Vahrenkamp

Man-Chung F Chang

A (GaAs-resident) application specific monolithic microwave integrated circuit (ASMMIC) is fabricated through the use of footprints that include a portion of the metallization through which the circuit components within the wafer are to be interconnected. The metallization is a three layers structure, the first two layers of which include strategically arranged reactance circuit components (MIM) capacitors. A first of the three metal layers is formed on a first surface of the substrate which contains a plurality of semiconductor device regions and conductive material for ohmic contact to the regions, so that portions of the first metal layer are in ohmic contact with the conductive material. The first metal layer provides the bottom plate of the MIM capacitors. A dielectric layer, which serves as the dielectric insulator of the MIM capacitors, is formed on second portions of the first metal layer. A second, intermediate metal layer is selectively formed on the second portions of the first metal layer, to provide top plate segments of MIM capacitors. Personalization of the footprint is effected by an air bridge metal layer interconnecting the first and second metal layers and thereby semiconductor device regions of the semiconductor structure with capacitive reactance elements formed by the first and second metal layers.

Three metal personalization of application specific monolithic microwave

A single-level photoresist process is used to make metal-semiconductor field-effect transistors (MESFETs) having more uniform threshold voltages. An N.sup.- layer is formed in a semi-insulating semiconductor, followed by formation of a dummy gate using a single-level photoresist process. Using the dummy gate as a mask, ions are implanted to form an N.sup.+ region. The length of the dummy gate is then reduced by plasma etching. A dielectric is deposited over the N.sup.+ region, the N.sup.+ /N.sup.- interface, and the exposed portion of the N.sup.- layer. The dummy gate is lifted off to define a self-aligned, submicron gate opening. The gate opening on the N.sup.- layer is reactive ion etched to obtain the desired threshold voltage, and covered with a Schottky gate metal deposit.

Process for manufacturing metal-semiconductor field-effect transistors

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Colorado Springs, CO, United States of America

Dennis A Williams