International Business Machines Corporation

Dennis A Schmidt

Anthony M Palagonia

John Edward Cronin

Bernadette Ann Pierson

Patricia E Marmillion

Richard Alan Haight

Michael Straight Hibbs

Alfred Wagner

Timothy E Neary

Jacek G Smolinski

Dennis M Hayden

Brian J Grenon

Raymond E Rochefort

J Peter Levin

Claude Louis Bertin

William R Tonti

Wayne John Howell

Howard L Kalter

James Marc Leas

Jerzy Maria Zalesinski

Gordon Arthur Kelley

Bruno Roberto Aimi

Patricia McGuinnes Marmillion

Andre Conrad Forcier

Janak G Patel

Clifford Owen Morgan, Iii

Philip Nicholas Theodoseau

Patricia McGuinness Marmillion

An integrated circuit is provided that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.

Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality

An integrated circuit that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.

An electrically activated fuse with a high melting point heater element in series with a low melting point fusible link. The heater element has a higher resistivity and larger cross-sectional area than the fusible link in order to withstand heat that the heater element generates bringing the fusible link to its melting point. Fuse dimensions (width and length) are each between 0.1 and 2.0 microns, with a thermal mass of the heater element being sufficient to melt the fusible link.

Micro fusible link for semiconductor devices and method of manufacture

An apparatus and method are provided that remove sufficient heat from both SOI and non-SOI semiconductor devices to prevent the devices from overheating during operation. A plurality of thermally conductive pads such as electrically conductive studs are coupled to a first side of a semiconductor device having circuit elements formed thereon. The thermally conductive pads also are coupled to a substrate comprising an apparatus for extracting heat from the thermally conductive pads. The apparatus for extracting heat from the thermally conductive pads preferably comprises one or more metallic planes. A module cover having a thermally conductive path formed therein also may be coupled between the apparatus for extracting heat and a heat sink to further aid in heat removal from the semiconductor device. Thermally conductive pads may be coupled between the semiconductor device and I/O pins of the substrate to improve heat dissipation via the I/O pins.

Method and apparatus for removing heat from a semiconductor device

In a silicon on insulator technology, cooling channels in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer, where the junction regions are separated from the substrate by an insulating layer. In a second embodiment, thermal conductors in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer where the junction regions are separated from the substrate by an insulating layer. Optionally, either the cooling channels or the thermal conductors may be enlarged such that a plurality of devices may be cooled by a single cooling channel or thermal conductor.

Cooling method for silicon on insulator devices

A method of repairing defects on masks includes the step of providing a coating on the mask to prevent damage to clear regions of the mask from laser ablation splatter, laser ablation caused quartz pitting, laser deposition staining, and FIB caused gallium staining. The coating is a metal, a polymer, or a carbon material. The coating is formed on clear regions of the mask as well as either over or under the light absorbing material of the mask. A coating comprising a thin copper layer significantly improves imaging with the ion beam while protecting clear regions of the mask from FIB stain. A coating formed of a photosensitive polymer is used to etch opaque defects. While wanted opaque regions adjacent an opaque defect are also etched in this etch step, these created clear defects are then repaired in a subsequent FIB deposition step while a copper coating protects adjacent clear regions from FIB stain. In another embodiment, opaque defects are repaired with a short pulse duration laser without damage to underlying quartz or adjacent clear regions while avoiding the need for a coating.

Methods for repair of photomasks

Method for repair of photomasks

Integrated Circuit ('IC') chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

Methods for precise definition of integrated circuit chip edges

Stacked three-dimensional devices can be prepared by stacking wafers as an alternative to stacking individual devices. Chip regions are formed on several wafers with each chip region being surrounded by a separation region, such as an insulator filled trench. The wafers are then stacked with the chip regions in alignment. Aligning the wafers can be facilitated using notched regions in the periphery of the wafers. The wafers are then joined together by lamination. After laminating the stacks of wafers, stacks of chips are separated by etching, dicing or other processes, which separate out stacked chip devices from the stacked wafer at the chip separation regions. The process allows several stacked chip devices to be manufactured simultaneously.

Method for stacked three dimensional device manufacture

A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity. The second conductive level includes islands of strap conductors that electrically interconnect the isolated conductors of the first conductive level. The first conductive level and a second conductive level are constructed of different conductive material which may be separately etched so that the second conductive level may be removed without affecting this first conductive level.

Fabrication, testing and repair of multichip semiconductor structures

Growing community of inventors

South Burlington, VT, United States of America

Dennis A Schmidt