Analog Devices,inc.

Analog Devices Global

Analog Devices International Unlimited Company

Analog Devices Global Unlimited Company

Analog Devices Technology

Dennis A Dempsey

Colin Gerard Lyden

Thomas G O'Dwyer

Tudor M Vinereanu

Oliver James Brennan

Hanqing Wang

GuangYang Qu

Patrick C Kirby

Tony Yincai Liu

Shurong Gu

Alan Walsh

John Jude O'Donnell

Dermot G O'Keeffe

Fergus John Downey

Donal P Geraghty

Donal Bourke

Eoin Edward English

Stefan Marinca

Michael C W Coln

Gavin Patrick Cosgrave

Mark Murphy

Roderick McLachlan

Seamus Paul Whiston

Denis Martin O'Connor

Michael G Tuthill

Junbiao Ding

Martin Gerard Cotter

Michael E Harrell

Sean B Brennan

Johan H Mansson

James Thomas Sheeran

Alan Gillespie

Christopher Matthew Gorman

Murat Demirkan

Michael D Keane

Ivan Bucoy Santos

Michael C Lynch

David J Rohan

Andrew Christopher Linehan

Zahit Evren Kaya

Ken Bryan Fulgosino Fabay

Christian Steffen Birk

Fintan M Leamy

Harvey T Mercado

Helen Stapleton

Junbiao s/O Ding

John Jude O'DONNELL

Dermot O'Keeffe

A configurable output stage for a DAC channel can include an output stage that can receive an analog output from a DAC and outputs a signal to an output terminal. The output stage can be configurable between a voltage mode and a current mode. In the voltage mode, the output stage can supply the analog signal to the output terminal as a voltage signal. In the current mode, the output stage can supply the analog signal to the output signal as a current signal. The output stage can receive user input to select the desired mode. Consequently, an integrated circuit can be implemented with multiple DAC channels, each having the configurable output stage. A user can choose how many channels they want to operate in a voltage output mode, and how many channels they want to operate in a current output mode, depending on their individual requirements.

DAC with configurable output stage

A circuit supply system includes a main digital to analog converter (DAC) circuit to produce a direct current (DC) output level at a system output; a feedback circuit path connected to the system output; a primary control circuit path connected to the feedback circuit path and configured to regulate the DC output level at the system output using the main DAC circuit and the feedback circuit path; and a secondary control circuit path connected to the feedback circuit path and configured to add a non-DC signal component to the DC output level and regulate the non-DC signal component using the feedback circuit path.

Closed loop DAC artifact generation

The present disclosure relates to an integrated circuit with at least a first channel and a second channel. Each channel includes at least a DAC. The integrated circuit also includes a number of circuit elements interconnected between the channels. The circuit elements can be changed between a short circuit state and an open circuit state. Normally, each channel will operate independently of one another, using only the circuit components in its respective channel. However, the circuit elements are arranged to allow a user to combine part of the second channel with the first channel to improve the functionality and performance of the first channel. In particular, a state of the circuit elements can be chosen to combine components of the second channel with the first channel. For example, components (e.g. a sub-stage) of the second channel can be connected in parallel with corresponding components (e.g. a corresponding sub-stage) of the first channel. This may reduce the number of available channels, since the second channel can no longer be used as an independent channel. However, the performance of the first channel is enhanced. The presence of the circuit elements allow an end user to decide whether to sacrifice channel count for performance enhancements. For example, the user can provide user input to the integrated circuit to select how the channels are interconnected. Moreover, the integrated circuit does not use additional redundant circuitry to improve the first channel, and rather takes components from the second channel. As such, the integrated circuit can have a reduced size.

Configurable DAC channels

A digital technique to reduce or minimize switching in a DAC by using a partial DAC data ignore switching mode. In the partial DAC data ignore switching mode, a control circuit compares first and second data, such a first and second digital words, and operates corresponding switches only when the first data differ from the second data. The techniques are applicable to many types of DACs, including voltage output DACs, current output DACs, variable resistance DACs, digital rheostats, digital potentiometers, digiPOTs.

Digital-to-analog converter glitch reduction techniques

The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths. In one example, the center of the channel away from the edges has a first doping concentration of a first conductivity type, and the sides of the channel along the channel edges have a second doping concentration of the first conductivity type, where the second doping concentration is greater than the first doping concentration. In another example, the dielectric layer is thicker over the sides of the channel and thinner over the center of the channel. In another example, regions of the substrate below the sides of the channel have a higher doping concentration than a region of the substrate below the center of the channel. In some examples, the FET structure has both the dielectric layer of different thicknesses and the different doping concentrations in the channel and/or the substrate.

Hybrid field-effect transistor

Techniques for generating a diagnostic waveform for a sensor are provided. In an example, a control circuit for an electrochemical sensor can include power supply inputs configured to receive a supply voltage, a first signal generator configured to receive control information and to generate a first signal on a first output using the supply voltage and the control information, a second signal generator configured to receive the control information and to provide a second signal on a second output, using the supply voltage and the control information. An output voltage between the first output and the second output, in a diagnostic mode of operation of the control circuit, can include a periodic signal having a peak-to-peak voltage greater than the supply voltage.

Diagnostic waveform generator for a sensor

A closed loop switch control system and a corresponding method is provided for controlling an impedance of a switch. The switch, which usually comprises a transistor switch, may be part of an external circuit. The system comprises the switch and a control unit coupled to the switch. The control unit is configured to regulate an impedance of the switch to a reference impedance while also enabling a fast switch response time. This is achieved by configuring the control unit to have a frequency response comprising a plurality of dominant poles and at least one zero.

Closed loop switch control system and method

A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N&#x2212;1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2&#x3c0; radians or a multiple thereof, where N is greater than 1.

Control circuit for use with a four terminal sensor, and measurement system including such a control circuit

The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string.

Digital-to-analog converter transfer function modification

Many electronic circuits rely on the ratio of one component to other components being well defined. Current flow in component can warm the component causing its electrical properties to change, for example the resistance of a resistor may increase due to self-heating as a result of current flow. The present disclosure provides a way to reduce temperature variation between components so as to reduce electrical mismatch between them or the consequences of such mismatch. This is important as even a change of resistance of, for example, 20-50 ppm in a resistor can result in non-linearity exceeding the least significant bit value of a 16 bit digital to analog converter.

Integrated circuit with on chip variation reduction

Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.

Digital-to-analog converter (DAC) termination

The noise power of an amplifier or buffer can increase towards the unity gain crossover frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.

Amplifier with noise control and a digital to analog converter with reduced noise bandwidth

A multiple impedance string, multiple output digital-to-analog converter (DAC) circuit that can include a shared coarse resolution DAC, two first fine resolution DACs to receive outputs of the MSB DAC, and a multiplexer to multiplex outputs of the first and second fine resolution DACs to output terminals. The multiplexer can be configured to interchange coupling of the outputs of the first and second fine resolution DACs using one or more MSBs.

Multiple string, multiple output digital to analog converter

A buffer is provided where a part of the buffer is implemented in switched capacitor or other analog discrete time processing circuitry and a dynamic response characteristic, such as an effective gain or charge transfer coefficient between the input stage and an output stage is digitally controllable. This means that the buffer can be driven as if it was a system controlled by, for example a three (3) term controller, giving rise to greater, digital flexibility in tailoring the buffer's transient response.

Buffer, and digital to analog converter in combination with a buffer

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Newport, Ireland

Dennis A Dempsey