Imec Vzw

Imec

Deniz Sabuncuoglu Tezcan

Eric Beyne

Yann Civale

Bart Swinnen

Philippe Soussan

Luc Haspeslagh

Nicolaas Tack

Yunlong Li

Nga Phuong Pham

Bart Vereecke

Piet De Moor

Gauri Karve

John Slabbekoorn

Antonia Malainou

According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed. The method results in a hybrid wafer comprising a planar top layer formed of the material of the continuous layer with one or more islands embedded therein, the top layer of the islands being formed by the top layer of the active material portion of the one or more tiles.

Method of producing hybrid semiconductor wafer

A Microelectromechanical Systems (MEMS) device combining a MEMS layer and a Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuit (IC), and its fabrication method is provided. The fabrication method includes: processing the MEMS layer on a first semiconductor substrate, the MEMS layer including one or more movable structures and one or more anchor structures; processing one or more first contacts on the first semiconductor substrate, each first contact being processed into one of the anchor structures and being configured to bias that anchor structure; processing the CMOS IC on a second semiconductor substrate; processing one or more second contacts on the second semiconductor substrate, each second contact being connected to the CMOS IC; and bonding the first semiconductor substrate to the second semiconductor substrate such that each first contact directly contacts one of the second contacts. The method can allow fabricating the MEMS device without vapor HF etching. The method can further enable zero level packaging, fusion bonding, a C-SOI approach, and high-vacuum sealing. An integrated zero level hermetic packaging MEMS device can be realized based on fusion bonding of moisture resistant materials. Further, Cu/dielectric bonding and electrical connections to individual parts of the MEMS device are allowed, in order to apply isolated voltages.

Fabrication method for a MEMS device

An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. The second multi-layer structures each have a bottom and a top reflective structure and a spacer layer arranged therebetween. The spacer layer has a thickness such that the multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation. The bottom and top reflective structures include a stack of alternating layers of a first and a second material. Thickness and/or material of the alternating layers of the first multi-layer structure differ from thickness and/or material of the alternating layers of the second multi-layer structure.

Integrated circuit and method for manufacturing integrated circuit

A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at least one second contact plug underneath the metal pad and in electrical contact therewith. At least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device.

Semiconductor device having through-substrate vias

A method for producing a GaNLED device, wherein a stack of layers comprising at least a GaN layer is texturized, is disclosed. The method involves (i) providing a substrate comprising on its surface said stack of layers, (ii) depositing a resist layer directly on said stack, (iii) positioning a mask above said resist layer, said mask covering one or more first portions of said resist layer and not covering one or more second portions of said resist layer, (iv) exposing said second portions of said resist layer to a light source, (v) removing the mask, and (vi) bringing the resist layer in contact with a developer comprising potassium, wherein said developer removes said resist portions that have been exposed and texturizes the surface of at least the top layer of said stack by wet etching said surface, in the areas situated underneath said resist portions that have been exposed.

Method for producing a GaNLED device

A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

Method for fabricating through substrate vias

Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.

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Neerwinden, Belgium

Deniz Sabuncuoglu Tezcan