Hewlett-packard Development Company, L.P.

Denise Man

Elias Gedamu

David Marshall

Eric Richard Stubblefield

Oguz Ertekin

Eilas Gedamu

Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit.

Built-in self-test emulator

One embodiment of a method comprises retrieving test data corresponding to test results from a plurality of fuses, each one of the plurality of fuses residing on a different one of a plurality of semiconductor devices and each one of the plurality of fuses having a common location on the semiconductor devices, determining from the test data which of the plurality of fuses are defective fuses, and specifying on an output report the common location of the determined defective fuses when a number of the defective fuses are at least equal to a predefined portion of the plurality of fuses.

System and method for indication of fuse defects based upon analysis of fuse test data

A system for automatically routing power in an integrated circuit, the system comprising memory for storing data defining a representation of an integrated circuit having a power contact and a power connection, and logic configured to analyze the data and to automatically route power from the power connection to the power contact.

System and method for automatically routing power for an integrated circuit

One embodiment of a method for analysis of cache array test data comprises retrieving test results for a current period of time for a first plurality of storage elements and for a historical period of time for a second plurality of storage elements; determining a plurality of attributes for each of the first storage elements and the second storage elements based upon the test results, the attributes comprising one of a good condition, a defective condition, a repairable condition and a repaired condition; determining a plurality of attribute statistics corresponding to the attributes of the first storage elements and the second storage elements; and generating an output report indicating at least two of the attribute statistics of the first storage elements and the second storage elements.

System and method for analysis of cache array test data

Disclosed are a heat dissipation computer and method. In one embodiment, a heat dissipation apparatus comprises a heat sink that is adapted to receive a processor mounted thereto, the heat sink comprising an internal chamber that is adapted to receive a fluid flow that removes heat from the heat sink. In one embodiment, a method for dissipating heat generated by a processor comprises forcing fluid through an internal chamber formed within a heat sink to which the processor is mounted, forcing the fluid from the internal chamber of the heat sink through at least one hollow prong that extends from the heat sink and that is in fluid communication with the internal chamber of the heat sink, and forcing fluid over exterior surfaces of the at least one hollow prong.

Heat dissipation apparatus and method

Systems and methods are described for sharing signals across a common metal trace on a single metal layer of an integrated circuit. The signals are time division multiplexed across the common metal trace such that a single metal layer of an integrated circuit is used to multiplex signals to and from a poly-silicon layer, reducing utilization of upper metal layers of the integrated circuit.

Multiplexing system and method for crossing signals on a single metal layer of an integrated circuit

An embodiment of the invention provides a circuit and method for reducing power in dynamic circuits. A large single pre-charge FET is used to pre-charge the pre-charge nodes of all dynamic logic blocks contained in a plurality of dynamic logic blocks. The large single pre-charge FET replaces all smaller individual FETs that normally would be used. Because smaller FETs typically have more subthreshhold leakage than larger FETs, the overall subthreshhold leakage is reduced. The large pre-charge FET only replaces smaller pre-charge FETs that have the same pre-charge signal going to their gates.

Growing community of inventors

Fort Collins, CO, United States of America

Denise Man