Texas Instruments Corporation

Denis R Beaudoin

Mihir Narendra Mody

Andre Szczepanek

Amritpal Singh Mundra

Niraj Nandan

Shashank Dabral

Ritesh Dhirajlal Sojitra

Gang Hua

Iain Craig Robertson

Chunhua Hu

Venkateswar Reddy Kowkutla

Thomas Anton Leyrer

Eric Robert Hansen

Gregory Lee Christison

Gregory Raymond Shurtz

Brian Jason Karguth

Samuel Paul Visalli

Michael J Hanrahan

Serge Bernard Lasserre

Daniel Brad Wu

Rajasekhar Reddy Allu

Lewis Nardini

Sriramakrishnan Govindarajan

Jose Luis Flores

Jason A T Jones

Michael A Denio

Akila Subramaniam

Mark Adrian Bryans

Jayant Thakur

Stephen Busch

Abhishek Shankar

Santhanakrishnan Badri Narayanan

William S Egr

Patrick Kruse

Marouane Berrada

James H Kennedy

Gregory Guyotte

Jose M Menendez

An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

Methods and apparatus to estimate consumed memory bandwidth

A technique for image processing, comprising: receiving input image data, wherein the image data is companded into a first bit depth, wherein the image data includes incomplete color values for pixels of the image data, and wherein the image data is associated with a first color space, interpolating the image data to generate color values for the incomplete color values for pixels of the image data, expanding the image data from the first bit depth to a second bit depth, wherein the color values of the expanded image data have a linear dynamic range, and wherein the second bit depth is higher than the first bit depth, converting the color values for pixels of the expanded image data from the first color space to a second color space, and compressing the color values for pixels of the image data to a third bit depth, the third bit depth lower than the second bit depth, and wherein the compressed color values have a nonlinear dynamic range.

High precision color processing for wide dynamic range sensors

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect 'OSI' model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network

A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.

Universal and adaptive de-mosaicing (CFA) system

An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

Independent operation of an ethernet switch integrated on a system on a chip

A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

Fault tolerant synchronizer

A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

Method and system for in-line ECC protection

An electronic circuit () includes one or more programmable control-plane engines () operable to process packet header information and form at least one command, one or more programmable data-plane engines () selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor () coupled to such a data-plane engine () and such a control-plane engine (). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Cryptographic engine, scheduler, packet header processor, ingress interfaces, and buffers

Packet accelerator ingress communication processor peripheral streaming interface, scheduler, buffer

Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network

Packet-processing with CPPI DMA streaming interface ingress and egress ports

Growing community of inventors

Missouri City, TX, United States of America

Denis R Beaudoin