Digital Equipment Corporation

Advanced Micro Devices Corporation

Nvidia Corporation

Ati Technologies Ulc

Compaq Computer Corporation, Inc.

Other

Hewlett-Packard Development Company, L.p.

Denis J Foley

David Martin Fenwick

Stephen R Van Doren

Mark Douglas Hummel

David W Hartwell

Ricky C Hetherington

Elbert Bloom

Alexander J Branover

Maurice B Steinman

Samuel Hammond Duncan

Glenn A Dearth

Marvin A Denman

John R Feehrer

Dennis K Ma

Brian Kelleher

Stephen David Glaser

Vyas Venkataraman

Stephen R VanDoren

Eric Tyson

Ram Gummadi

Zeeshan S Syed

Jonathan Owen

Michael Osborn

Dale R Keck

Serag M GadelRab

Bin Du

Dave Hartwell

Ljubisa Bajic

Jonathan Mercer Owen

Daniel Wissell

Richard B Watson, Jr

James Lyall Esliger

Denis Rystsov

Douglas J Burns

Robert M Mondor

E William Bruce, Ii

Philip Tousignant

Anthony F Vivenzio

Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Techniques for an efficient fabric attached memory

A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

System and method for early packet header verification

A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.

Processor bridge power management

The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.

Method and apparatus for securing digital information on an integrated circuit read only memory during test operating modes

A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

Method and apparatus for transitioning devices between power states based on activity request frequency

In certain systems, local requests require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request is present. If the associated information is present, a request is placed in an output request queue to service the local request. If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.

Latency hiding for a memory management unit page table lookup

An integrated circuit () may receive a boot loader code () via a debug access port (), wherein a boot logic is operative to block, upon a reset () of the programmable processor () from the debug access port (), commands and to the programmable processor from the debug access port, while still allowing the reset () command and while allowing write access to memory () to receive the boot loader code image () written to memory (). The boot logic also blocks commands to the memory subsystem () from the debug access port and turns off write access to memory () after allowing the boot loader code image () to be written. The boot logic validates the boot loader code image () by performing a security check and jumps to the boot loader code image () if it is valid, thereby allowing it to run on the programmable processor (). The boot logic may be logic circuits, software or a combination thereof.

Integrated circuit with secure boot from a debug access port and method therefor

An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.

Apparatus and method for reducing power consumption by an integrated circuit

The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.

Method and apparatus for securing digital information on an integrated circuit during test operating modes

One disclosed system comprises a first channel for routing at least one of a plurality of cables in a first direction; a second channel for routing said at least one cable in a second direction; and a plurality of teeth spaced apart from one another and disposed in one of said first channel and said second channel, said teeth positioned to create spaces in-between said plurality of cables before said at least one cable transitions from said first direction to said second direction.

System and method for routing cables

In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.

Apparatus for determining memory bank availability in a computer system

A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for requesting control of the system bus, prior to determining whether such control is required, by asserting the associated system bus control request signal. A computer system including the system bus and at least two such commander modules coupled to the system bus and means for arbitrating for control of the system bus where the arbitrating means are coupled to and responsive to the system bus control request signals.

Distributed early arbitration

A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison. The data bus sequencer further includes means for driving the sequence tag for an address and command transaction to which a data transaction is associated on the data bus. Consistency check means includes means for tracking data transactions occurring on a data bus, and means for comparing tracked data transactions to sequence number tags driven on the data bus. The consistency check means indicates an error condition in response to the comparison if the sequence number tag most recently driven on the data bus is not equal to the counted number of data transactions which have occurred on the data bus.

Distributed data bus sequencing for a system bus with separate address

Growing community of inventors

Shrewsbury, MA, United States of America

Denis J Foley