Societe Anonyme De Telecommunications

Sat (societe Anonyme De Telecommunications)

Denis F Cointot

Patrice R Langlois

Andre H Cauderlier

Guy De Passoz

A binary-to-bipolar converter converts two binary signals into positive and negative bipolar pulses alternately corresponding to a '1' logic state of two binary signals. The bipolar pulses are defined by the low output impedance states of two transfer gates. The main object of the invention is to reduce the transient trailing of the rear edges in the bipolar pulses. This can be obtained by delaying the drop from the low impedance state to the high output impedance state by means delaying control signals on the transfer gates, or by an integrator circuit applying calibrated pulses onto the output of the transfer gates, in response to the rear edges of the '1' logic states in the binary signals. The converter also calibrates the rise times of the bipolar pulses and allow the use of CMOS circuits upstream of the converter.

Binary-to-bipolar converter

A digit rate reducing system for PCM signals comprises a predictor stage, an automatic gain control stage, and a quantizer stage for adaptive quantizing. The predictor stage includes a predictor and a subtractor for subtracting from a sample x.sub.n of the PCM input signal a predicted signal x.sub.pn derived from preceding samples. The subtractor provides a difference signal d.sub.n representing prediction error to the automatic gain control (AGC) stage. A divider in the AGC stage divides the difference signal d.sub.n by m, providing a divided signal e.sub.n to the quantizer stage. In this last stage, a quantizer encodes the divided signal e.sub.n into a signal Y.sub.n of reduced rate. The predictor uses a first adder which receives the predicted signal x.sub.pn and a reconstituted signal d.sub.n derived from the reduced rate signal Y.sub.n ; a plurality of shift registers and associated multipliers; and a second adder connected to the outputs of the multiplier. Shift registers T.sub.1 . . . T.sub.N are coupled to the output of the first adder, and provide a series of delayed signals to multipliers M.sub.1 . . . M.sub.N for multiplying by respective coefficients a.sub.i (n) derived from the preceding samples. At least one of the predictor coefficients a.sub.i (n) is applied to the quantizer, whereby the type of coding is adapted to the statistical properties (ie, the conditional probability distribution curve) of the PCM input signal.

Device for digit rate reduction of PCM-signals

A predictor stage for a digital processing system for sampled and PCM coded signals in the form of a sequence of samples x.sub.n, having first transmission means and first reception means for forming a predicted sample x.sub.pn. Second transmission means are also provided for subtracting said sample x.sub.pn predicted from said sample x.sub.n coming in at the transmission side, and deriving therefrom a difference sample d.sub.n representing the prediction error. The first transmission means has a recursive structure, with each predicted sample x.sub.pn being derived from the samples d.sub.n, d.sub.n-1, d.sub.n-2 . . . etc. previously obtained at the output of the second transmission means. The first reception means has a transverse structure, with each sample x.sub.pn being derived at the reception side from the difference samples d.sub.n, d.sub.n-1 . . . , previously received. The samples x.sub.pn predicted at the reception side are added to the difference samples within the second reception means.

Predictor stage for a digit rate reduction system

A method of receiving a codirectional interface digital signal coded in bipolar form, each data bit being represented by means of four bits (1,1,0,0) for a binary '1' and (1,0,1,0) for a binary '0', a polarity alternation being effected every bit with a violation of polarity at each octet, comprising the steps of: separating the interface signal into its positive and negative components; producing a rectified signal from the said components; deriving from the rectified signal a bit timing signal; deriving the decoded data signal from the rectified signal and the timing signal; deriving from said components a signal representing the alternations of polarity; deriving from this latter signal and from the bit timing signal an octet timing signal; and comparing in phase the bit timing signal and the polarity alternation signal, a pulse for rephasing the bit timing signal being produced when the states of these two signals do not coincide at the time of a polarity alternation.

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Paris, France

Denis F Cointot