Mitsubishi Electric Corporation

Mitsubishi Electric R&d Centre Europe B.v.

Denis Cousineau

Eric Lavillonniere

David Mentre

It is disclosed a PLC Program analysis method where a program is translated into a program model in a logical framework, from which properties are determined. Said properties coupled with interlocking properties are verified by an automated solver. If contraposition of a property is satisfiable, counter-examples representative of model's inputs and internal memory values is provided. Counter-examples are translated into error initial configurations of said model. Execution of the model is simulated with said model error initial configurations, and error intermediary configurations of said model simulation are recorded up to said property violation. Error initial and intermediary configurations of said original program are derived from error initial configurations of said model and error intermediary configurations of said model simulation and displayed. An apparatus for executing said method is provided.

Method for analyzing a Programmable Logic Controller program

It is disclosed a PLC Program analysis method where a program (PROG) is translated (TRANS) into a model (MOD) in a logical framework, from which properties (Prop) are determined. Said properties coupled with user specifications (IntProp) are verified by an automated solver (SMT). If contraposition of a property (Prop) is satisfiable, counter-examples (PROOF NOK) representative of model inputs and internal memory values is provided. Counter-examples (PROOF NOK) are translated into error initial configurations (IniConf) of said model. Execution of the model is simulated (EXE) with said model error initial configurations (IniConf), and error intermediary configurations (AST-IntConf) of said model simulation are recorded up to said property violation. Error initial and intermediary configurations (Lad-IniConf, Lad-IntConf) of said original program (PROG) are derived from error initial configurations (IniConf) of said model and error intermediary configurations (AST-IntConf) of said model simulation and displayed. An apparatus for executing said method is provided.

Method, computer program and apparatus for analysing a programmable logic controller program

A method () to generate test suite for a source-code (). The method comprises: a) implementing a structural analysis () of said source-code () to obtain a completed source-code () including: &#x2014;parsing the source-code, &#x2014;addition of annotations defining tests objectives, &#x2014;generation of stubs; b) implementing at least one semantic analysis algorithm including categorizing each set of tests objectives as satisfied, impossible to satisfy or unsatisfied; c) feeding a first list () with satisfied test cases; d) feeding a second list () with test objectives impossible to satisfy, e) implementing at least one mathematical optimization algorithm () on parts corresponding to unsatisfied test objectives; &#x2014;identifying test cases () that satisfy at least a part of said test objectives, &#x2014;feeding said first list of set of test cases with them, &#x2014;categorizing said test objectives as satisfied; f) providing a test suite comprising the two lists.

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Rennes, France

Denis Cousineau