Cadence Design Systems, Inc.

Google Inc.

Denis Baylor

Hurley Song

Matthew Robert Rardon

Clifford L Biffle

Michial Allen Gunter

Charles Ross

Marcus Felipe Fontoura

Asim Shankar

Sascha Richter

Zigmars Rasscevskis

Douglas Lee Taylor Rohde

Andras Csomai

Mahesh S Palekar

Daniel N Meredith

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

Synchronization in multi-chip systems

A hybrid-sharded index includes document-sharded posting lists and term-sharded posting lists. Implementations include systems and methods for updating a hybrid-sharded index. For example, a method may include receiving updates to the hybrid-sharded index and generating, at a first leaf node, replacement posting lists and change information for a respective second leaf node. The method may also include dividing the replacement posting lists into portions, a portion having associated change information and being associated with a respective one of the second leaf nodes and sending the portions to respective leaf nodes. At a particular leaf node of the second leaf nodes, the method includes merging a received portion into an updated posing list portion, swapping the updated posting list portion into memory. During the swap, the change information and the updated posting list portion are used to respond to a query with an older version of the hybrid-sharded index.

Indexing system

A hybrid-sharded index includes document-sharded posting lists and term-sharded posting lists. Implementations include systems and methods using a distributed hybrid-sharded index. For example, a method may include receiving, at a root node, a query having a first term and a second term and determining, that the first term is term-sharded. The method may also include retrieving a term-sharded posting list for the first term from a first leaf node that stores the term-sharded posting list and determining, at the root node, a second leaf node that stores a document-sharded posting list for the second term. The method may include sending the second term and a sub-set of documents from the term-sharded posting list to the second leaf node, the sub-set being documents assigned to the second leaf node; and generating a search result using a response received from the second leaf node.

In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.

Methods for physical layout estimation

In one embodiment of the invention, a method is disclosed including receiving a netlist of an integrated circuit design; executing a first copy of an integrated circuit design program with a first processor associated with a first memory space to independently perform work on a first portion of the integrated circuit design; and executing a second copy of the integrated circuit design program with a second processor associated with a second memory space to independently perform work on a second portion of the integrated circuit design; wherein the second memory space is independent of the first memory space.

Systems and methods for super-threading of integrated circuit design programs

Methods and systsm for physical layout estimation

Software and systems for physical layout estimation

In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.

Methods for reduced test case generation

Physical layout estimator

Systems and methods for reduced test case generation

Systems and methods for super-threading

Growing community of inventors

Cupertino, CA, United States of America

Denis Baylor