Acco Semiconductor, Inc.

Acco Corporation

Other

Denis A Masliah

Alexandre G Bracale

Francis C Huin

Patrice J Barroul

Christophe Boyavalle

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Electronic circuits including a MOSFET and a dual-gate JFET

A power amplifier of the present invention comprises a first cascode including a MOSFET and a JFET and a first capacitor electrically connected between the source and the drain of the JFET. Two such power amplifiers in parallel form a differential power amplifier. In the differential amplifier a second capacitor can be electrically connected between the source and the drain of the second JFET. Another differential power amplifier comprises a first capacitor electrically connected between the gate of the first MOSFET and the source of the second MOSFET, and a second capacitor electrically connected between the gate of the second MOSFET and the source of the first MOSFET. Some of these differential power amplifiers also include capacitors electrically connected between the sources and the drains of the JFETs.

Capacitive cross-coupling and harmonic rejection

An IGFET device includes: &#x2014;a semiconductor body having a major surface, &#x2014;a source region of first conductivity type abutting the surface, &#x2014;a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, &#x2014;an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, &#x2014;a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.

IGFET device having an RF capability

RF switching devices are provided that alternatively couple an antenna to either a transmitter amplifier or a receiver amplifier. An exemplary RF switching device comprises two valves, one for a receiver transmission line between the antenna and the receiver amplifier, the other for a transmitter transmission line between the antenna and the power amplifier. Each valve is switchably coupled between ground and its transmission line. When coupled to ground, current flowing through the valve increases the impedance of the transmission line thereby attenuating signals on the transmission line. When decoupled from ground, the impedance of the transmission line is essentially unaffected. The pair of valves is controlled such that when one valve is on the other valve is off, and vice versa, so that the antenna is either receiving signals from the power amplifier or the receiver amplifier is receiving signals from the antenna.

RF switches

A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.

High breakdown voltage double-gate semiconductor device

An IGFET device includes: &#x2014;a semiconductor body () having a major surface, &#x2014;a source region () of first conductivity type abutting the surface, &#x2014;a drain region () of the first conductivity-type abutting the surface and spaced from the source region with a channel () therefrom, &#x2014;an active gate () overlying the channel and insulated from the channel by a first dielectric material () forming the gate oxide of the IGFET device, &#x2014;a dummy gate () positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.

IGFET device having a RF capability

A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate may be a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. Because an individual junction gate has an intrinsically high breakdown voltage, the breakdown voltage of the double-gate semiconductor device is greater than the breakdown voltage of an individual MOS gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.

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St-Germain-en-Laye, France

Denis A Masliah