Huawei Technologies Co., Limited

Dengben Wu

Yu Zhang

Yixiang Liao

Junjie Wang

Xin Qiu

Baifeng Yu

Zhiming Zhu

Ligang Chen

Xiaoxin Xu

The present invention provides a data write method and a solid-state drive array. The solid-state drive array is based on a RAID system and includes n solid-state drives. Before to-be-written data is written into the solid-state drive array, the to-be-written data is divided into n data blocks that are in a one-to-one correspondence with the n solid-state drives. After the n data blocks are all stored into the corresponding solid-state drives, FTL update of the n data blocks is performed, to complete write of the to-be-written data. If the solid-state drive array is powered off during storage of the n data blocks, because FTL update of the data blocks is not performed, all the n data blocks fail to be written into the solid-state drive array, thereby ensuring atomicity of write operations of the n data blocks.

Data write method and solid-state drive array

The present application relates to a storage device operation control method, a storage device, and a management node. The method includes: receiving at least one request sent by at least one management node; and when one of the at least one request is a permission application request, determining, according to a current permission status, whether to assign operation permission to a management node that sends the permission application request; or when one of the at least one request is an operation request, determining, according to a current permission status, whether a management node that sends the operation request has operation permission, and performing an operation according to the operation request when the management node that sends the operation request has the operation permission. This avoids a conflict caused by simultaneously performing an operation on a storage device by multiple management nodes, and prevents successive serial operations from being interrupted.

Storage device operation control method, and storage device

A method and an apparatus for implementing compatibility of different processors are provided. The method includes: in a standby state of a board, obtaining configuration information and a type of a processor on the board; and if a processor type in the configuration information is different from the type of the processor, updating, according to the processor, a parameter that is relevant to the processor and is in the configuration information, and changing FLASH memory chip selection configuration in order to connect the connector to a FLASH memory for storing a BIOS program of the processor.

Method and apparatus for selecting bios program for a processor

The present invention discloses a method and an apparatus for node hot-swapping, which simplify the node hot-adding procedure, and improve the operation efficiency of the hot-adding procedure. The present invention includes: obtaining, by a server from a baseboard management controller BMC of a node device to be added, static hardware information of the node device to be added, and storing it into a storage device of the server, where the static hardware information is obtained through an out-band channel by the BMC of the node device to be added; receiving, by the server, a node hot-adding command sent by a user, where the hot-adding command carries identifier information of the node device to be added; obtaining the static hardware information of the node device to be added corresponding to the identifier information from the storage device; and adding, according to the static hardware information, the node device to be added.

Method and apparatus for node hot-swapping

The present invention relates to a computer system and a clock configuring method. The computer system comprises at least two nodes, wherein each of the at least two nodes includes a selecting module and a CPU, inputs to the selecting module of any node comprise a clock of the node and a clock output from other node, and an output terminal of the selecting module is connected to the CPU and an input terminal of the selecting module of other node; the computer system further comprises a clock controlling module, whose output terminal is connected to a control terminal of the selecting module to control the clocks of the at least two nodes to be the same clock. When clocks of plural nodes are abnormal, the computer system can still normally operate as long as there is a normal clock in the computer system.

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Hangzhou, China

Dengben Wu