International Business Machines Corporation

Delbert Raymond Cecchi

Curtis Walter Preuss

Charles C Hanson

Jack Allan Mandelman

Toshiharu Furukawa

Daniel Mark Dreps

John Steven Mitby

Gerald Keith Bartley

Kenneth Michael Valk

Gregory Scott Still

David Otto Lewis

David W Siljenberg

Daniel N De Araujo

Michael Launsbach

Nghia Van Phan

Thomas James Osten

Richard Lee Donze

David Peter Swart

Donald Joseph Schulte

Philip T Wu

Marius V Dina

Charles C Hansen

Glenn W Sellers

Linda S Herman

Jeffrey A Collett

Balsha R Stanisic

Hyung S Kim

Thomas J Osten

A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same

A method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. A separate power distribution is provided for coupling a positive voltage supply rail to the N well and a ground voltage supply rail to the P well of the CMOS circuit. At least one sensor monitors current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. A switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected.

Method and apparatus for detection and prevention of bulk CMOS latchup

A differential amplifier for providing common-mode rejection while providing differential-mode amplification includes an active differential amplification element electrically coupled to a first input signal, a second input signal and an output signal. The active differential amplification element is also electrically coupled to a first voltage and to a different second voltage. A passive bias element is electrically coupled to the active differential amplification element. The passive bias element is capable of biasing the active differential amplification element so that the active differential amplification element operates in a saturation mode. The active differential amplification element thereby generates the output signal so that the output signal corresponds to a voltage difference between the first input signal and the second input signal.

CMOS low voltage high-speed differential amplifier

Methods and apparatus are provided for implementing a receiver capable of receiving signals in simultaneous bi-directional current mode differential links. The receiver comprises a resistor-summing network and a differential amplifier. The resistor-summing network can also comprise capacitors for the purpose of attenuating high-frequency noise at the differential amplifier. The high-frequency noise can arise from impedance discontinuities in the signal paths or from differences in rising or falling transition times between the data driver and the replica driver in the links.

CMOS receiver for simultaneous bi-directional links

A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.

Dual mode analog differential and CMOS logic circuit

A system for transmitting and receiving data between the near end to the far end of a transmission line. The system has simultaneous bi-directional (SBIDI) drivers and receivers for high performance over well behaved transmission lines. The SBIDI drivers and SBIDI receivers are enabled and disabled by logic inputs. A unidirectional (UNI) receiver is connected in parallel with each SBIDI receivers. Logic insures that the SBIDI and UNI receivers are not enabled at the same time. When desired, the SBIDI receivers are disabled and the UNI receivers enabled and signaling is done unidirectional. The current level in the SBIDI drivers may be modified in response to mode compensation signals to improve signal to noise in the unidirectional mode and to compensate for losses in the simultaneous bi-directional mode. The system may be integrated into all I/O's for maximum design flexibility.

Simultaneous bi-directional I/O system

A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals. In one embodiment the differential receiver circuit further includes an inhibit circuit configured receive an inhibit control signal and to drive the p-channel devices gated to the first amplifier node and the n-channel devices gated to the second amplifier node to cutoff when the inhibit control signal is in a specified inhibit state. The inhibit circuit is preferably further configured to provide a low impedance path between the first amplifier node, the second amplifier node, and the feedback node when the inhibit control signal is in a specified functional state.

Cascaded differential receiver circuit

Enclosure services in a computer system having a Host computer and at least one Target device, are provided on a functional path, which is preferably a relatively high-speed, point-to-point serial bus between the Host computer and the at least one Target device. The at least one Target device and the Host computer each have a full power operational mode and an auxiliary power mode. The Host computer generates enclosure services commands and sends them to the at least one Target device on the functional path. The at least one Target device can receive and respond to the enclosure services commands, even when in the auxiliary power mode.

Simple enclosure services (SES) using a high-speed, point-to-point, serial bus

A resistance circuit includes an off-chip resistor having a precision resistance; a plurality of on-chip switchable resistors, each of which is capable being switched so as to be coupled in parallel to a nominal resistor; and a resistance comparison unit. The resistance comparison unit compares a plurality of on-chip comparison resistors to the off-chip resistor and couples a number of the on-chip switchable resistors to the nominal resistor so that the combined resistance of the parallel combination of the nominal resistor and the coupled on-chip switchable resistors is within a predetermined range of the precision resistance.

Active trim circuit for CMOS on-chip resistors

A digital data waveform is precompensated for attenuation through a transmission medium. First, during actual initial power-on or upon reconfiguration of a digital communication system, attenuation characteristics of the transmission medium are actually measured. The attenuation characteristics can be measured by measuring the length of the transmission medium, measuring the error rate of test packets having known frequency, measuring the slope of a test pulse at two separate threshold voltages, and/or measuring the error rate of a random signal packet. Upon determination of the magnitude of the attenuation characteristic, one of a plurality of registers corresponding to the range of values of the attenuation characteristic is selected. These registers have a plurality of pre-emphasis coefficients to be applied in the driver to each bit of a series of digital signal pulses as determined by the transition history of at least three sequential bits. Thus, dynamic and in-situ pre-emphasis can be determined and applied to signals to compensate for attenuation in the transmission network attenuation.

Driver with in-situ variable compensation for cable attenuation

An echo cancellation circuit for neutralizing signal reflections in a differential link interface, and a method for achieving the same. The differential link interface includes a line driver that generates a line drive signal and a replica driver for generating a replica signal that mirrors the line drive signal within the differential link. The echo cancellation circuit includes a slope adjustment device within the replica driver for temporarily altering the slope of the replica line drive signal during a signal reflection at the output of the line driver, such that the amplitude of the replica signal corresponds to the amplitude of the line drive signal during the signal reflection.

Echo cancellation circuit for a Bi-directional current mode link

A Complementary Metal Oxide Semiconductor (CMOS) current mode differential link with precompensation is provided. The Complementary Metal Oxide Semiconductor (CMOS) bi-directional current mode differential link with precompensation includes a CMOS driver receiving a data input and having an output coupled to a transmission line. A CMOS replica driver receives the data input and provides a replica driver output substantially equal to the CMOS driver output. A CMOS receiver is coupled to both the transmission line and replica driver output. The CMOS receiver subtracts the replica driver output from a signal at the transmission line. The CMOS driver and the CMOS replica driver include a plurality of parallel current sources. Each of the current sources is arranged to send positive or negative current through a load responsive to an applied control signal. The use of the plurality of parallel current sources allows the CMOS driver to effectively implement precompensation. The output current of the CMOS driver is a function of a data bit and at least one previous data bit.

CMOS bi-directional current mode differential link with precompensation

A digital data waveform precompensated for off-chip cable attenuation includes peaks with exponential tails at signal transitions. A driver output stage generating the waveform includes an output transistor pulling the output to a peak voltage level when an input goes high. After a delay, a transistor closes a feedback loop containing a resistive load, exponentially changing the voltage level of the output to a final voltage level. A complementary output transistor pulls the output to a ground voltage level when the input goes low, with a transistor closing a feedback loop containing a resistive load for exponential change of the output to a final voltage level. The separate resistive paths equalize the time constant of the exponential tails despite a difference in the gate capacitances of the output transistors. The received waveform after cable attenuation exhibits pulse shapes closer to the predefined pulse shapes on which a receiver is designed to operate.

Off chip driver with precompensation for cable attenuation

A method and apparatus that can test self-timed parallel interfaces operating at system speed. An output stage is provided for queuing a test packet and providing the test packet to an input stage. The packet contains a data bit stream and error detection code such as cyclic redundancy check code. The input stage is coupled to the output stage and receives the test packet to determine the correctness of the data bit stream. On the input stage, the error detection code verifier recalculates the error detection code and compares the recalculated error detection code with the error detection code attached to the data bit stream to determine the correctness of the data bit steam. The output queue has a first input port for receiving data from drivers on the interface and a second input port for receiving a pseudo random data bit stream. A pseudo random data generator generates a pseudo random data bit stream. The data bit stream may be packetized according to a predetermined protocol. An off-chip signal of the output stage may be provided to the inputs of the input stage to produce an on-chip copy of off-chip data.

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Rochester, MN, United States of America

Delbert Raymond Cecchi