Newport Media, Inc.

Dejun Wang

Hassan Elwan

Adel Fanous

Amr M Fahim

Ahmed A Emira

Edward Youssounan

An electrical circuit includes a first transistor having a first source, a first drain, and a first gate, whereby the first transistor receives an input voltage through the first gate. An output voltage terminal outputs voltage from the first transistor and is connected to the first drain. A second transistor includes a second source, a second drain, and a second gate, whereby the second transistor receives a bias voltage through the second gate, and wherein the first source is connected to the second drain. A first capacitor is connected to the first source, the second source, and the second drain. An inductor is connected to the first drain. A second capacitor is connected in parallel with the inductor and further connected to the first drain.

Multi-phase voltage controlled oscillator using capacitance degenerated single ended transconductance stage and inductance/capacitance load

An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.

High voltage electrostatic discharge clamp using deep submicron CMOS technology

A portable memory device dimensioned and configured as any of a removable flash memory card, a USB flash drive, and a jump drive and a method of wireless communication, wherein the portable memory device comprises a single housing component; a data storage component within the single housing component; and a wireless receiver operatively connected to the data storage component and within the single housing component, wherein the wireless receiver is adapted to receive wireless signals comprising radio signals, satellite signals, TV signals, and Bluetooth&#x2122; specification signals, and wherein the wireless receiver is adapted to wirelessly communicate with a LAN. The portable memory device may further comprise an interface component adapted to connect to a host computing device. Preferably, the TV signals comprise mobile TV signals.

Device, system, and method for providing wireless data access, digital TV access, radio, and storage capability

A radio frequency wide band amplifier having a noise that does not exceed a threshold value, and a linearity better than a threshold value. The radio frequency wide band amplifier architecture includes a first stage amplifier and a second stage amplifier. The second stage amplifier includes an input source resistor (R) that receives an input voltage signal, a feedback resistor (R) directly connected to the input source resistor, a p-type metal-oxide-semiconductor (PMOS) transistor directly connected to the input source resistor. The PMOS transistor receives an output from the input source resistor. A n-type metal-oxide-semiconductor (NMOS) transistor directly connected to the input source resistor. The NMOS transistor receives an output from the input source resistor. A lumped output resistor (R) that receives an output from the feedback resistor, the PMOS transistor, and the NMOS transistor. A terminal of the lumped output impedance is connected to ground.

High linearity, low noise, wide bandwidth amplifier/buffer

A system and method for performing voltage to current conversion, the system comprising of a first set of devices that senses the input voltage signal through its input terminal and replicates said input voltage across a second set of devices which then converts said replicated input voltage signal to an output current signal; a third set of devices that transfers the output current signal to output terminals; a differential feedback loop comprising an amplifier positioned between a first one of the first set of devices and a first one of the third set of devices; and a common mode feedback loop that regulates the output average voltage to a reference voltage.

High linearity voltage to current conversion

A continuous time sigma-delta analog-to-digital converter (CT &#x3a3;&#x394;ADC) including an integrator, which includes an operational amplifier having at least one input terminal that receives an input signal, a feedback mechanism operatively connected to the operational amplifier, at least one capacitor coupled to the operational amplifier and the feedback mechanism, a reset switch coupled to the at least one capacitor, the operational amplifier, and the feedback mechanism, and a single directional voltage-to-current converter coupled to the input terminal. The single directional voltage-to-current converter translates a differential signal voltage only to a differential signal current. The reset switch resets the feedback mechanism. The single directional voltage-to-current converter behaves a one-directional resistor. The integrator prevents current generation when there is a non-linear disturbance at the input terminal of the operational amplifier. The single directional voltage-to-current converter clips an input current that exceeds a threshold value.

Continuous time sigma-delta analog-to-digital converter with stability

A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.

Low noise, low power, high linearity differential amplifier with a capacitive input impedance

A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.

Optimized gain filtering technique with noise shaping

A continuous time-sigma delta (CT-SD) data converter comprising a loop filter includes a first integrator having a first loop filter coefficient and a second integrator operatively coupled to the first integrator, the second integrator having a second loop filter coefficient, a modulator coupled to the loop filter, a reset switch coupled to the second integrator, a first peak detector operatively coupled in series with the second integrator to indicate an instability condition of a signal level exceeding a first threshold at an output of the second integrator, a second peak detector adapted to detect an input signal level to the CT-SD data converter, and a digital engine coupled to the first peak detector.

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Irvine, CA, United States of America

Dejun Wang