Csmc Technologies Fab2 Co., Ltd.

Southeast University

Csmc Technologies Fab1 Co., Ltd.

Dejin Wang

Weifeng Sun

Longxing Shi

Siyang Liu

Kui Xiao

Song Zhang

Chi Zhang

Jiaxing Wei

Yan Jin

Li Lu

Zhibin Liang

Shengli Lu

Guipeng Sun

Shen Xu

Sheng Li

Ningbo Li

Xinyi Tao

Minggang Chen

Boyong He

Tao Liu

Rui Jiang

Wanqing Yang

Qichao Wang

Ling Yang

Zhiyong Wang

Ran Ye

Jingjing Ma

Rengang Qin

A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

Heterojunction semiconductor device with low on-resistance

A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

Lateral double-diffused metal oxide semiconductor field effect transistor

Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor Sand a clamp switching transistor S; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor S; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.

System and method for controlling active clamp flyback converter

A flash device and a manufacturing method thereof. The method comprises: providing a substrate, and forming, on the substrate, a floating gate polycrystalline layer, a floating gate oxide layer, and a tunneling oxide layer; wherein the floating gate polycrystalline layer is formed on the substrate, the floating gate oxide layer is formed between the substrate and the floating gate polycrystalline layer, a substrate region at one side of the floating gate polycrystalline layer is a first substrate region, a substrate region at the other side of the floating gate polycrystalline layer is a second substrate region; forming, on the tunneling oxide layer, located in the first substrate region, a continuous non-conductive layer, the non-conductive layer extending to the tunneling oxide layer at a side wall of the floating gate polycrystalline layer; and forming, on the tunneling oxide layer, a polysilicon layer.

Flash device and manufacturing method thereof

A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

Gallium nitride power device and manufacturing method thereof

A manufacturing method for a flash device. A manufacturing method for a flash device, comprising: providing a substrate; forming sequentially, on the substrate, a floating gate (FG) oxide layer, an FG polycrystalline layer, and an FG mask layer; etching, at the FG location region, the FG polycrystalline layer and the FG mask layer, forming a window on the FG mask layer, and forming a trench on the FG polycrystalline layer, the window being communicated with the trench; performing second etching of the side wall of the window of the FG mask layer, enabling the width of the trench located on the FG polycrystalline layer to be less than the width of the secondarily-etched window located on the FG mask layer; and oxidizing the FG polycrystalline layer, enabling the oxide to fill the trench to form a field oxide layer; and etching an FG having sharp angles.

Manufacturing method for flash device

Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer () covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer () is 700 angstroms &#xb1;10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device.

Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method

A capacitor and a method of fabricating thereof are provided. A structure of low pressure tetraethyl orthosilicate&#x2014;low pressure silicon nitride&#x2014;low pressure tetraethyl orthosilicate is used in the capacitor to replace the oxide-nitride-oxide structure of the existing capacitor; the capacitor has a relatively high unit capacitance value. Furthermore, the structure of low pressure tetraethyl orthosilicate&#x2014;low pressure silicon nitride&#x2014;low pressure tetraethyl orthosilicate is fabricaited by low pressure chemical vapor deposition method at relatively low temperature; thus the heat produced in the whole process is relatively low, which is insufficient to make the semiconductor device shift or make the gate metal layer or the metallized silicon layer peel off. Accordingly, the capacitor and the method of fabricating the capacitor of the present invention can be well applied in the process of the 0.5 &#x3bc;m PIP capacitor or below 0.5 &#x3bc;m.

Capacitor and preparation method thereof

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Jiangsu, China

Dejin Wang