Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Dejan S Milojicic

Paolo Faraboschi

John Paul Strachan

Sai Rahul Chalamalasetti

Yuan Chen

Vanish Talwar

Martin Foltin

Sergey Serebryakov

Alan Messer

Catherine Graves

Chris I Dalton

Zhikui Wang

Daniel Juergen Gmach

Kirk M Bresniker

Cullen Edwin Bash

Robert S Schreiber

Moray McLaren

Alexander Leslie Richardson

Moritz Josef Hoffmann

Timothy F Forell

Kimberly Keeton

Derek Steven Schumacher

Andrew Ray Wheeler

Michael S Woodacre

Subramoniam N Iyer

Gerd Zellweger

Philippe Bernadat

Guangrui Fu

Aditya Dhakal

Izzat El Hajj

Alexander Merritt

Douglas L Voigt

Geoffrey Ndu

Chandrasekar Venkatraman

Amit S Sharma

Stephen B Lyle

Peter Piet

Ira Greenberg

Keith Packard

Brian Cox

Sudarsun Kannan

Gourav Rattihalli

Alan G Nemeth

Abhishek Gupta

Norman Paul Jouppi

Zhichen Xu

Sharad Singhal

Duncan Roweth

Xue Liu

Dwight L Barron

Doe Hyun Yoon

Sheng Li

Praveen Yalagandula

Kevin T Lim

Mehmet Kivanc Ozonat

Can Li

Akhil Sahai

Patrick Charles McGeer

Carey Huscroft

Qiong Cai

Adrian Shaw

Jon Christopher Connelly

Andy Brown

Rajnish Kumar

Soumendu Bardhan

Donald E Bollinger

Lukas Humbel

Steve Ko

Chetan Shankar

Vahe Poladian

Guilherme James De Angelis Fachini

Ninad Sanjay Hogade

Gustavo Henrique Rodrigues Pinto Tomas

Eitan Frachtenberg

Francisco Plinio Oliveira Silveira

Tobias Pfandzelter

Kaiwen Cao

Giacomo Pedretti

Jack Yanxin Li

Pedro H R Bruel

Rolando Pablo Hong Enriquez

Gabriel Parmer

Dazhao Cheng

Helen W Cheung

Leonid Azriel

Systems and methods are provided for a dynamic communication architecture that can include decentralized heterogenous accelerators, and an operation of mapping corresponding decentralized virtualized accelerators. The mapping of corresponding decentralized virtualized accelerators is performed on top of, for example, a memory-mapped multi-accelerator communication architecture to enable effective and flexible sharing of data. The mapping can be dynamically adjusted with regard to the workload running by analyzing workflow communication.

Dynamic communication architecture for decentralized heterogenous accelerators

Systems and methods are provided for implementing an iterative function deployment in a Function-as-a-Service (FaaS) computing environment. For example, the system may receive a request to execute a program and convert machine-readable code from the request into functions that are deployable in the FaaS computing environment. The system may determine a first deployment of the functions that defines scheduling and execution tasks, and also an execution metric by a trained prediction model. The system may adjust execution of the plurality of functions and also adjust the execution metric in a second deployment. The system may implement the second deployment at run-time, such that the machine-readable code from the request is executed by the computing components of the FaaS infrastructure in accordance with the second deployment.

Automated program conversion for heterogeneous and FaaS computing with minimal human intervention

Systems and methods are provided for an accelerator system that includes a baseline (production) accelerator, optimizing accelerator, and control hardware accelerator, and an operation of alternatingly switching the production/optimizing accelerators between production and optimizing. With two production/optimizing accelerators, at any given point in time, one accelerator adapts while another accelerator processes data. Once the second accelerator starts doing a better job (e.g., has adapted to data drift), the accelerators change their modes, and the trainable accelerator becomes the 'optimized' one. The accelerators do this non-stop, thus maintaining redundancy, providing expected quality of service (QoS) and adapting to data/concept drift.

Self-adaptable accelerators having alternating production/optimizing modes

A first NIC monitors a key-value cache associated with an LLM executed by a compute node that includes the first NIC and an accelerator. The key-value cache is stored in a memory associated with the accelerator. Responsive to detecting that the key-value cache is updated by the accelerator, the first NIC transfers a copy of the key-value cache update to a remote storage node. The key-value cache is deleted from the memory after the query is inferred. Responsive to receiving a follow-up user query, the first NIC determines a storage location on the remote storage node that stores the key-value cache corresponding to the user query and sends a KV-cache-transfer request to a second NIC on the remote storage node, the KV-cache-transfer request specifying the storage location, thereby facilitating the second NIC to transfer the key-value cache corresponding to the user query from the specified storage location to the memory.

Efficient key-value cache management for large language models

A cache is used for efficiently storing a graph structure. The graph cache may be used in a computing system to accelerate processing of a graph by a graph neural network, and is different than a general-purpose memory of the computing system. Embeddings for the nodes of a graph are stored in the memory of the computing system, while the structure of the graph is stored in the graph cache. The graph cache may include a content addressable memory array, which may be suitable for efficiently representing a graph structure.

Graph cache

Systems and methods are provided for a modular switch system that comprises disaggregated components, plugins, and managers that enable flexibility to adjust the dynamic configuration of a switch system. This can create modularity and customizability at different times of the lifecycle of the currently configured switch system.

Dynamically modular and customizable computing environments

A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

Acceleration of model/weight programming in memristor crossbar arrays

The disclosure provides for systems and methods for improving bandwidth and latency associated with executing data requests in disaggregated memory by leveraging usage indicators (also referred to as usage value), such as 'freshness' of data operators and processing “gravity” of near memory compute functions. Examples of the systems and methods disclosed herein generate data operators comprising near memory compute functions offloaded proximate to disaggregated memory nodes, assign a usage value to each data operator based on at least one of: (i) a freshness indicator for each data operators, and (ii) a gravity indicator for each near memory compute function; and allocate data operations to the data operators based on the usage value.

Freshness and gravity of data operators executing in near memory compute in scalable disaggregated memory architectures

In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

Resistive and digital processing cores

Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to 'warm' resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.

Optimal dispatching of Function-as-a-Service in heterogeneous accelerator environments

In exemplary aspects, a golden data structure can be used to validate the stability of machine learning (ML) models and weights. The golden data structure includes golden input data and corresponding golden output data. The golden output data represents the known correct results that should be output by a ML model when it is run with the golden input data as inputs. The golden data structure can be stored in a secure memory and retrieved for validation separately or together with the deployment of the ML model for a requested ML operation. If the golden data structure is used to validate the model and/or weights concurrently with the performance of the requested operation, the golden input data is combined with the input data for the requested operation and run through the model. Relevant outputs are compared with the golden output data to validate the stability of the model and weights.

Resiliency for machine learning workloads

Optimal dispatching of function-as-a-service in heterogeneous accelerator environments

A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.

Methods and systems for computing in memory

Growing community of inventors

Palo Alto, CA, United States of America

Dejan S Milojicic