Motorola Corporation

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Dejan Mijuskovic

David Edward Bien

David A Hayner

Ouelid Abdesselem

Jeffrey A Porter

Liviu Chiaburu

Joel Cameron Beckwith

Yizhen Lin

Jerome Romain Enjalbert

Steven D Millman

Keith L Kraver

Thierry Dominique Yves Cassagnes

Deyou Fang

Philip W McEntarfer

Frederick H James

Martin J Bayer

A circuit comprises an amplifier, a first switch arranged between an amplifier input and an amplifier output, a first capacitor, a first resistor, a second switch, a third switch, a first converter coupled to the first amplifier output, a register storing a last digital value, a second converter converting the stored last digital value into a corresponding voltage value, and a control circuit. The control circuit charges the first capacitor to the corresponding voltage value by coupling a second converter output to a second capacitor terminal and switching on the first switch, or by coupling the second converter output to the first capacitor terminal and switching on the third switch; switches on the first switch and the second switch for providing the input voltage signal to the first capacitor; and switches on the third switch for determining a subsequent digital value of the converted output amplifier signal.

Filtered sampling circuit and a method of controlling a filtered sampling circuit

An angular rate sensor () includes a single drive mass () and distributed sense masses () located within a central opening () of the drive mass (). The drive mass () is enabled to rotate around the Z-axis () under electrostatic stimulus. The sense masses () are coupled to the drive mass by spring elements () such that oscillatory rotary motion () of the drive mass imparts a linear drive motion () on the sense masses. The distributed sense masses form two pairs of sense masses, where one pair senses X- and Z-axis angular rate and the other pair senses Y- and Z-axis angular rate. The sense masses are coupled to one another via a centrally located coupler element () to ensure that the sense masses of each pair are moving in anti-phase.

Angular rate sensor having multiple axis sensing capability

A microcontroller-based method and apparatus are described for generating one or more amplitude and frequency selectable low frequency pilot tone signals (PT) that are injected into an embedded MEMS sensor () and mixed signal ASIC () and then recovered at the microcontroller () to compute or measure various gyro parameters during operational use of the device with no down time or interference with normal operations.

Generation, injection and use of pilot tones for gyro system characterization

A low pass filter circuit includes an amplifier having a single-ended output. A first line and a second line are arranged to receive a differential signal. A first switch selectively connects the first line to a first input of the amplifier in a first cycle of operation having a first observation window. A second switch selectively connects the second line to a second input of the amplifier in a second cycle of operation having a second observation window that is at least partially coincident with the first observation window. A signal measuring stage that is supplied with a modulated input signal generates the differential signal. The signal measuring state has an input switch to reverse a polarity of the differential signal applied to the first and second lines of the low pass filter circuit.

Low pass filter circuit

A circuit comprises a first phase detector, a second phase detector, and combinational logic. The first phase detector is for detecting a phase difference between a rising edge of a first clock signal and a rising edge of a second clock signal, and for providing a first difference signal indicating the phase difference. The second phase detector is for detecting a phase difference at a time of a falling edge of the first clock signal and a time of a falling edge of the second clock signal, and for providing a second difference signal indicating the phase difference. The combinational logic is coupled to receive the first difference signal and the second difference signal, and for preventing the second difference signal from being provided when the first difference signal is being provided.

Phase/frequency detector for a phase-locked loop that samples on both rising and falling edges of a reference signal

An inertial sensor has a transducer with a sense resonator. The sense resonator is oscillated. A signal responsive to the oscillation is provided. A first baseband signal and a second baseband signal are provided responsive to the signal responsive to the oscillation of the sense resonator. A signal for controlling a resonance frequency of the sense resonator is provided responsive to performing a Goertzel algorithm on the first baseband signal and the second baseband signal. One use of controlling the resonance frequency is to control an offset between the resonance frequency of the sense resonator and the frequency of the oscillation of drive masses in the sense resonator. Using the Goertzel algorithm is particularly efficient in controlling the resonance frequency.

MEMS inertial sensor with frequency control and method

A device () includes a sensing element () having drive nodes () and sense nodes (). Parasitic capacitance () is present between drive node () and sense node (). Likewise, parasitic capacitance () is present between drive node () and sense node (). When a drive signal () is applied between drive nodes (), a parasitic current () between drive and sense nodes () and a parasitic current () between drive and sense nodes () is created due to the parasitic capacitances (). A capacitive network () is coupled between the drive node () and the sense node () to create a correction current () through capacitive network () that cancels parasitic current (). Likewise, a capacitive network () is coupled between the drive node () and the sense node () to create a correction current () through capacitive network () that cancels parasitic current ().

Sensor device with reduced parasitic-induced error

Apparatus and methods are provided for multiplier circuits having reduced phase shift. A multiplier circuit comprises an input node for an input signal and an output node for an output signal. A first multiplier is coupled to the input node and has a first multiplier output, wherein the first multiplier multiplies the input signal by a first signal to produce a second signal at the first multiplier output. A second multiplier is coupled to the output node and is matched to the first multiplier. The second multiplier multiplies the output signal by a third signal to produce a fourth signal at a second multiplier output. An amplifier is coupled to the first multiplier output and the second multiplier output and produces the output signal at an amplifier output coupled to the output node based upon the second signal and the fourth signal.

Matched multiplier circuit having reduced phase shift for use in MEMS sensing applications

Embodiments of capacitive sensors () and methods for reducing noise in capacitive sensors are provided. Embodiments of capacitive sensors include a gain stage (), a capacitive sensor output, and an active filtered-sampling stage (). The an active filtered-sampling stage includes a first resistive element () coupled to the gain stage output, a second resistive element () coupled to the capacitive sensor output, a node () between the first and second resistive elements, and a switch () selectively coupling the first node to an integrator circuit (), where the integrator circuit is coupled to the capacitive sensor output.

Capacitive sensors including gain and active-filtered sampling stages

A circuit is provided which generates a first output signal and a second output signal. The circuit includes a reference signal input having a reference value, a first positioning circuit, and a second positioning circuit. The first positioning circuit generates the first output signal responsive to a first differential input signal and the reference signal, and the second positioning circuit generates the second output signal responsive to a second differential input signal and the reference signal. In one implementation, the positioning circuits may be reversed peak detectors. A minimum value of the first output signal and a minimum value of the second output signal are positioned along a common axis at values greater than or equal to the reference value.

Logic threshold acquisition circuits and methods using reversed peak detectors

A system and method is provided for bit eye center retraining. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively compares the location of the transitions to the expected locations to produce difference values, and combines pairs of difference values to determine when the sample point of the data stream needs to be adjusted.

Eye center retraining system and method

An apparatus and method are provided for reducing noise in a capacitive sensor (). One apparatus includes a gain stage () including an output, the gain stage configured to generate a first signal having a noise component and a second signal having a desired output component and the noise component, and a filtered-sampling stage () having an input coupled to the gain stage output, the filtered-sampling stage configured to sample the first signal, store the first signal, and subtract the first signal from the second signal to produce a desired output signal. A method includes generating a first signal having a first noise component of the gain stage (), storing the first signal (), generating a second signal comprising a desired output component and the first noise component (), and subtracting the first signal from the second signal to produce a first output signal having the desired output component ().

System and method for reducing noise in sensors with capacitive pickup

A transimpedance amplifier is provided which includes a feedback path. The feedback path includes a feedback resistor and a voltage generator. The feedback resistor has a parasitic capacitance associated therewith. The feedback resistor also has a first node at a first voltage. The voltage generator can be capacitively coupled to the feedback resistor at a second node via the parasitic capacitance. The voltage generator is configured to generate a second voltage at the second node which is substantially equal to the first voltage. This prevents a current from flowing through the parasitic capacitance thereby reducing and/or eliminating the effect of the parasitic capacitance on the transimpedance amplifier.

High bandwidth resistor

A method and circuit ( ) for dynamically adjusting the supply voltage (Vdd) in a digital circuit ( ) determines the propagation delay (tpd) of a signal along a signal path ( ) in the digital circuit and adjusts the supply voltage so that the determined propagation delay equals a predetermined period, such as the clock period of the clock signal (CLK) which clocks the digital circuit. the determined propagation delay equals the predetermined period, the adjusted supply voltage is applied to the digital circuit ( ). This technique can be used to optimise power consumption and processing capability.

Growing community of inventors

Chandler, AZ, United States of America

Dejan Mijuskovic