University of California

Dejan Markovic

Dejan Rozgic

Kang L Wang

Pedram Khalili Amiri

Asad A Abidi

Chengcheng Wang

Richard Dorrance

Hariprasad Chandrakumar

Fengbo Ren

Chih-Kong Ken Yang

Ali H Sayed

Kang-Lung Wang

Vaibhav Karkare

Itzhak Fried

Nanthia Suthana

Jiacheng Pan

Stefan Vlaski

Alireza Yousefi

Hawraa Salami

Sina Basir-Kazeruni

Biomedical implants in accordance with various embodiments of the invention can be implemented in many different ways. The implants can be configured to receive power and transmit data, both wirelessly and simultaneously. Such devices can be configured to receive power from an external source and transmit data, such as but not limited to recorded neural data and/or other biological data, to outside the body. In many cases, the data is transmitted to the device that delivers power to the implant. For example, the power and data transmission system can be implemented with a pair of transceivers. The implant transceiver can receive power wirelessly though an external transceiver while simultaneously transmitting data to the external transceiver. In several embodiments, both forward (power) and reverse (data) links use the same pair of inductive coils in the transceivers, one coil mounted in the implant and the other in the external unit.

Load-induced resonance-shift-keying modulation scheme for simultaneous near-field wireless power and data transmission through a pair of inductive coils

Many embodiments of the invention provide a neuromodulation system that includes a digital control unit (DCU) that activates a stimulation engine during active stimulation, a current mirror that includes two feedback loops including a first feedback loop with positive feedback (PF) made of an error amplifier Aand transistors Mand Mand a second feedback loop with a negative feedback (NF) made of the error amplifier Aand transistor M, and a high-voltage adaptive rail (V/V) to accommodate voltage drops across high electrode impedances.

Electrode agnostic, supply variant stimulation engine for implantable neural stimulation

Systems and methods for using near-field inductive coupling between an implanted system and an external transceiver are discloses. In several embodiments, the data link system is based on a free-running oscillator tuned by coupled resonators. The use of an oscillator-based power link can allow for stable power over different inductor distances, or coil distances. In some embodiments, the data link system includes receivers on both sides of the link, where each receiver is composed of a detector, such as but not limited to an analog front-end ('AFE'), and a clock and data recovery ('CDR') loop.

Systems and methods for low-power near-field-communication

Many embodiments provide an implant power management unit (IPMU) that includes a reconfigurable active rectifier (AR) for wireless power transfer (WPT), where the AR is configurable to operate in a plurality of different modes of operation, an adaptive load control (ALC) unit that accommodates power delivery with load requirements, where the ALC unit is configured to control AR voltage based upon a desired value, control circuitry that is configured to enable a full bridge rectifier in a regular mode of operation of the AR, a feedback circuit that adaptively generates offset current to compensate for switch delays in at least one active NMOS diode, and a feedback circuit that adaptively generates offset current to compensate switch delays in at least one active PMOS diode.

Load adaptive, reconfigurable active rectifier for multiple input multiple output (MIMO) implant power management

Neuromodulation systems in accordance with embodiments of the invention can use a feed-forward common-mode cancellation (CMC) path to attenuate common-mode (CM) artifacts appearing at a voltage input, thus allowing for the simultaneous recording of neural data and stimulation of neurons. In several embodiments of the invention, the feed-forward CMC path is utilized to attenuate the common-mode swings at V, which can restore the linear operation of the front-end for differential signals. In several embodiments, the neuromodulation system may utilize an anti-alias filter (AAF) that includes a duty-cycles resistor (DCR) switching at a first frequency f, followed by a DCR switching at a second frequency f. The AAF allows for a significantly reduced second frequency fthat enables the multi-rate DCR to increase the maximum realizable resistance, which is dependent upon the frequency ratio f/f.

High input impedance, high dynamic range, common-mode-interferer tolerant sensing front-end for neuromodulation systems

System and methods that cancel artifacts of stimulation signals from neural signals are disclosed. In several embodiments, the systems and methods determine a threshold value for the neural signal in the absence of artifacts. The threshold value can then be used to detect an artifact in received neural signals. In a number of embodiments, a template can be used to cancel an artifact from a neural signal in response to the neural signal being greater than the threshold value.

Systems and methods for reducing noise caused by stimulation artifacts in neural signals received by neuro-modulation devices

Signal recording sensor systems in accordance with embodiments of the invention include sensors capable of sensing and capturing electrophysiological signals in the presence of interference signals, an analog front-end including circuitry configured to record electrophysiological input signals as a voltage, and an analog to digital converter including a voltage-controlled-oscillator configured to convert the recorded analog electrophysiological input signal to a phase output. While such signal recording sensor systems can be used in the recording of biosignals and/or electrophysiological signals generated from living organisms, signal recording sensor systems in accordance with embodiments of the invention are not limited to recording biosignals and/or electrophysiological signals.

Saturation-tolerant electrophysical recording interface

A high dynamic range sensing front-end for bio-signal recording systems in accordance with embodiments of the invention are disclosed. In one embodiment, a bio-signal amplifier includes an input signal, where the input signal is modulated to a predetermined chopping frequency, a first amplifier stage, a parallel-RC circuit connected to the first amplifier stage and configured to generate a parallel-RC circuit output by selectively blocking an offset current, a second amplifier stage connected to the parallel-RC circuit that includes a second input configured to receive the parallel-RC circuit output and generate a second output that is an amplified version of the input signal with ripple-rejection. Further, the bio-signal amplifier can also include an auxiliary path configured for boosting input impedance by pre-charging at least one input capacitor. In addition, the bio-signal amplifier can also include a DC-servo feedback loop that includes an integrator that utilizes a duty-cycled resistor.

High dynamic range sensing front-end for neural signal recording systems

Systems and methods for restoring cognitive function are disclosed. In some implementations, a method includes, at a computing device, separately stimulating one or more of lateral and medial entorhinal afferents and other structures connecting to a hippocampus of an animal subject in accordance with a plurality of predefined stimulation patterns, thereby attempting to restore object-specific memories and location-specific memories; collecting a plurality of one or more of macro- and micro-recordings of the stimulation of hippocampalentorhinal cortical (HEC) system; and refining the computational model for restoring individual memories in accordance with a portion of the plurality of one or more of macro- and micro-recordings.

Systems and methods for restoring cognitive function

Thermoelectric energy harvesting systems in accordance with embodiments of the invention enable energy harvesting. One embodiment includes a thermoelectric energy harvesting (TEH) system comprising a TEH comprising a thin-film array-based TEH source; start-up mode circuitry comprising: an upper branch comprising: a mode switch configured to allow selection of the upper branch; an inductive-load ring oscillator (ILRO); a charge pump configured to receive an input from the ILRO and output current, where output current is utilized to charge an upper branch capacitor; a lower branch comprising: an inductor; an active diode configured to transfer energy stored in the inductor to an output capacitor; maximum-power-point tracking (MPPT) mode circuitry, where the MPPT loop comprises: a mode control unit; a gate controller; a clock generator configured to generate at least one control signal; an analog-domain MPPT unit configured to receive the at least one generated control signal.

Autonomous thermoelectric energy harvesting platform for biomedical sensors

Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine. The computing resources (cores and data-paths) can be reused across the entire OMP process resulting in optimal utilization of the PEs.

Scalable and parameterized VLSI architecture for compressive sensing sparse approximation

Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Fine-grained power gating in FPGA interconnects

Systems and methods for implementing boundary-less hierarchical networks including methods of generating such networks in accordance with embodiments of the invention are disclosed. In one embodiment, a hierarchical network in an integrated circuit that includes a plurality of computing elements, where the plurality of computing elements have M outputs and N inputs, and a plurality of switches arranged into stages of switches wherein the plurality of computing elements are connected to switches in a first stage, the switches in the first stage are connected to the plurality of computing elements and switches in a second stage, where the switches in the second stage are connected to the switches in the first stage, at least M+1 adjacent computing elements can connect to at least two nearest neighboring computing elements via a stage 1 switch, and every computing element can connect with every other computing element within the hierarchical network.

Systems and methods for switching using hierarchical networks

Voltage controlled magnetoelectric tunnel junction (MEJ) based content addressable memory is described which provides efficient high speed switching of MEJs toward eliminating any read disturbance of written data. Each cell of said CAM having two MEJs and transistor circuitry for performing a write at voltages of a first polarity, and reads at voltages of a second polarity. If the data searched does not equal the data written in the CAM, then the match line state is changed.

Read-disturbance-free nonvolatile content addressable memory (CAM)

Voltage controlled magneto-electric tunnel junctions (MEJ) and associated memory devices are described which provide efficient high speed switching of non-volatile magnetic random access memory (MeRAM) devices at high cell densities with multiple word access mechanisms, including a burst mode write of multiple words, and a back-to-back read of two words in consecutive clock cycles. In at least one preferred embodiment, these accesses are performed in a manner that prevents any possibility of a read disturbance arising.

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Los Angeles, CA, United States of America

Dejan Markovic