Telefonaktiebolaget Lm Ericsson (publ)

Rise Research Institutes of Sweden Ab

Dejan Kostic

Amir Roozbeh

Gerald Q Maguire, Jr

Alireza Farshin

Rebecca Steinert

Shaoteng Liu

Gerald Q Maguire Jr

Methods and systems for selective access to a processing unit are described. An electronic device that is coupled with the processing unit for processing packets is described. The electronic device is operative to receive a packet; determine based on one or more attributes of the packet that the packet is to be split; and responsive to determining that the packet is to be split, splitting the packet into a first portion and a second portion, where the first portion is to be processed by the processing unit and the second portion is to be stored without being processed by the processing unit; sending the first portion of the packet toward the processing unit for processing; and storing the second portion of the packet.

Method and system for efficient input/output transfer in network devices

Methods and systems for selective direct access to a processing unit of a network device are described. A network interface of the network device receives packets of a flow. The network interface determines based on attributes of the packets that the packets are to be directly sent to the processing unit. In response to determining that the packets are to be directly sent to the processing unit, they are directly sent to the processing unit for processing.

A memory allocator in a computer system comprising a plurality of CPU cores (-) and a first () and a second () memory unit having different data access times and wherein each one of the first and the second memory units is divided into memory portions wherein each memory portion (SLICE 0-3) in the second memory unit is associated with at least one memory portion (A-G) in the first memory unit, and wherein each memory portion in the second memory unit is associated with a CPU core. If at least a predetermined number of memory portions in the first memory unit being part of the available requested memory is associated with the memory portion in the second memory unit that is associated with the CPU core on which the requesting application is running, the requested available memory is allocated to the requesting application.

Memory allocation in a hierarchical memory system

Embodiments herein relates e.g., to a method performed by a first entity, for handling memory operations of an application in a computer environment, is provided. The first entity obtains position data associated with data of the application being fragmented into a number of positions in a physical memory. The position data indicates one or more positions of the number of positions in the physical memory. The first entity then provides, to a second entity, one or more indications of the one or more positions indicated by the position data for prefetching data from the second entity, using the one or more indications.

Entities, system and methods performed therein for handling memory operations of an application in a computer environment

A method and device for controlling memory handling in a processing system comprising a cache shared between a plurality of processing units, wherein the cache comprises a plurality of cache portions. The method comprises obtaining first information pertaining to an allocation of a first memory portion of a memory to a first application, an allocation of a first processing unit of the plurality of processing units to the first application, and an association between a first cache portion of the plurality of cache portions and the first processing unit. The method further comprises reconfiguring a mapping configuration based on the obtained first information, and controlling a providing of first data associated with the first application to the first cache portion from the first memory portion using the reconfigured mapping configuration.

Methods and devices for controlling memory handling

A method in a multi-core processing system which comprises a processor comprising at least a first and a second processing unit, a cache, common to the first and the second processing unit, comprising a first cache portion associated with the first processing unit and a second cache portion associated with the second processing unit, a memory, comprising a first memory portion associated with the first cache portion and a second memory portion associated with the second cache portion. The method comprises detecting that a data access criteria of the second memory portion is fulfilled, establishing that first data stored in the second memory portion is related to a first application running on the first processing unit, allocating at least a part of the first memory portion to the first application based on cache information, and migrating the first data to the part of first memory portion.

Methods and nodes for handling memory

Embodiments of the invention relate to computerized systems and computerized methods configured to optimize data transmission paths in a large-scale computerized network relative to reliability and bandwidth requirements. Embodiments of the invention further relate to computerized systems and methods that direct and control the physical adjustments to data transmission paths in a large-scale network's composition of computerized data transmission nodes in order to limit data end-to-end transmission delay in a computerized network to a delay within a calculated worst-case delay bound.

Growing community of inventors

Solna, Sweden

Dejan Kostic