Intel Corporation

Deif N Atallah

Richard C Beckett

Pak-Lung Seto

Nathan Marushak

Mark A Schmisseur

Eric J DeHaemer

Yan Xu

Mitchell A Kahn

A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include first circuitry and second circuitry. The first circuitry may be capable of performing at least one operation including, at least in part, generating check data based at least in part upon other data, regenerating the other data based at least in part upon the check data, and/or determining locations of the check data and the other data in storage. The second circuitry may be capable of controlling, at least in part, at least one interface to transmit from and/or receive at the integrated circuit the check data and/or the other data. Depending at least in part upon the selected mode of operation, the first circuitry may be either enabled to perform or disabled from performing the at least one operation.

Integrated circuit having multiple modes of operation

An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor, a bridge, and circuitry capable of coupling the bridge and the processor to a first bus and to a second bus. The first bus may be compatible with a first bus protocol, the second bus may be compatible with a second bus protocol, and the first and second bus protocols may be different from each other. The bridge may be capable of, in response at least in part to a request from the processor, preventing a command received at the bridge via the first bus from being forwarded from the bridge to the second bus. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Integrated circuit having processor and bridging capabilities

An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor and a switch. The switch may comprise one or more ports capable of being coupled to one or more segments external to the switch. The processor may be capable of issuing to the switch one or more commands indicating, at least in part, one or more protocols via which the one or more ports are to communicate and/or one or more forwarding characteristics of the switch. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Integrated circuit having processor and switch capabilities

A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include processor circuitry and interface circuitry. The processor circuitry may include a plurality of processor cores. The interface circuitry may be capable of communicating in accordance a plurality of different protocols. At least one of the processor cores may be capable of issuing a command to the interface circuitry to communicate in accordance with at least one of the plurality of different protocols that corresponds to the selected mode of operation of the integrated circuit.

A method according to one embodiment may include transmitting a frame from a transmitting device to a receiving device via a communication network of a data storage system, enabling an encoding operation of the transmitting device to encode decoded data into encoded data and transmitting the encoded data in the frame via the communication network if the receiving device has a decoding operation capable of decoding the encoded data into the decoded data, and disabling the encoding operation and transmitting the decoded data in the frame via the communication network to the receiving device if the receiving device does not have the decoding operation capable of decoding the encoded data into the decoded data. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Data encoding and decoding in a data storage system

Provided are a method, adaptor, system, and program for receiving a transmission at one of multiple connections. Information is maintained on storage interconnect architectures and transmission characteristics, wherein the storage interconnect architectures have different transmission characteristics. At least one transmission characteristic of the received transmission is determined and a determination is made from the information of the storage interconnect architecture associated with the determined transmission characteristic. The information on the determined storage interconnect architecture is used to process the transmission and determine a transport layer for the received transmission, wherein there is one transport layer for each supported transport protocol. The transmission is forwarded to the determined transport layer.

Adaptor supporting different protocols

Provided are a method, system, and program for processing a transmission from a first device to a second device. An identification transmission is received including an interface address from the first device. A determination is made as to whether the identification transmission indicates a recognized vendor identifier. An interface address of a third device is returned to the first device in response to determining that the identification transmission includes one recognized vendor identifier, wherein the third device relays transmissions between the first and second devices.

Managing transmissions between devices

The state of cached data may be modified without performing a tag comparison. Each cache line includes at least one attribute bit and at least one state bit. A processor issues an instruction requesting modification of the state of all cache lines associated with an attribute specified by the instruction. Qualifying logic modifies the state of a cache line as a function of the attributes stored in the cache line and the attribute specified by the instruction.

Method and apparatus for quickly modifying cache state

A system which is able to perform unaligned big endian and little endian accesses to memory with little or no added overhead to the system. In the preferred embodiment, the processor operates in little endian data format. The memory, however, can store data in big endian and little endian format in different memory regions. If an unaligned access is to be performed, the access requires translation to corresponding aligned memory accesses. However, if the processor operates in little endian format and accesses are to memory which store according big endian format, special code is required to perform proper translation of accesses. When the address generation unit of the processor detects an unaligned memory access, an unaligned signal is set which causes a microassist to initiate a microflow to execute microcode which performs the necessary translations for unaligned accesses. The address generation unit also sends the address to be access to the memory region table which maintains information regarding each memory region, including whether the region is big endian or little endian. The state bit indicative of the data format is logically combined with the unaligned access signal to generate an output which sets the state of the flag. The flag is then accessed by the microcode to determine the translation routine to process the memory access.

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Chandler, AZ, United States of America

Deif N Atallah