Freescale Semiconductor,inc.

Deeya Muhury

Sanjay Kumar Wadhwa

Kulbhushan Misri

Qadeer Ahmad Khan

Murugesan Raman

Pawan K Tiwari

A digital clock frequency multiplier () for increasing an input frequency of an input clock signal includes a generator () that receives the input clock signal and a high frequency digital signal. The generator () divides a count (N) of a number of cycles of the high frequency digital signal in one period of the input clock signal by a predetermined multiplication factor (MF) for generating an output clock signal. The output clock signal has a predetermined output frequency.

Digital clock frequency multiplier

A digital clock frequency doubler for increasing an input frequency of an input clock signal includes an input block, and a generator block. The input block receives the input clock signal, and generates a pulse signal having an ON period equal to the input clock signal period. The generator block is coupled to the input block. The generator block receives the pulse signal and divides a period of the pulse signal by a period of a high frequency digital signal and then generates an output clock signal with an output frequency that is about two times the input frequency.

Digital clock frequency doubler

A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion voltage is independent of the ramp rate of VDD. The POR circuit is shut off as soon as the reset signal is generated, thereby drawing zero steady state current from VDD. The re-arm time for the POR circuit is very small. The POR circuit does not reset the chip when there is a dynamic change in VDD.

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Deeya Muhury