Qualcomm Incorporated

Photometria, Inc.

Deepu John

Haitao Zhang

Brian K Butler

Mohammad Jafar Mohseni

Li Feng Zhang

Inyup Kang

Gilbert Christopher Sih

Daisuke Terasawa

Qiuzhen Zou

Jafar Mohseni

Way-Shing Lee

Hao Liu

Quaeed Motiwala

Sivarama Krishnan Venkatesan

Qiuzhen (Joe) Zou

David J Kriegman

Sanjay K Jha

Satya Prakash Mallick

Brian George

Jian Lin

Sudarsan Krishnan

Benjamin Cheadle

Charles E Sakamaki

Kevin Barnes

Prashant A Kantak

Vipanj B Patel

Kristine Anna Dougherty

Margaret Rose Ciafardini Kirkland

Isan A Doshi

Anuj Ojha

Quizhen Zou

A method includes receiving, at a device to be calibrated, a data packet from a second device that is directing the calibration. The data packet includes at least two segments, where each segment corresponds to at least one calibration instruction. The method includes conducting a calibration of the device according to the calibration instructions corresponding to the at least two segments.

Systems and methods of device calibration

A system and method for providing a personalized face chart. A digital image of the subject's face is obtained. A facial region of the digital image is identified. A line drawing is generated based on at least the facial region of the digital image.

System and method for providing a face chart

Techniques for efficient searching in asynchronous systems, such as W-CDMA, as well as multi-mode searching, are disclosed. In one aspect, step one and step three search are performed in a single search engine. In another aspect, a search engine is configurable to search the offsets of a slot in step one search, producing sequential hypothesis energies, and peak detecting and sorting those energies. In yet another aspect, the peak detector and sorter are configurable to perform step one searching or step three/multimode searching. Various other aspects of the invention are also presented. These aspects have the benefit of circuit area and search-time efficiency which translate into reduced costs, increased standby time, increased acquisition speed, higher quality signal transmission, increased data throughput, decreased power, and improved overall system capacity.

Steps one and three W-CDMA and multi-mode searching

A composite signal has two components, each carrying a stream of information that may be digital. In one application of a method according to an embodiment of the invention, at least one of the components is delayed such that a time relation between the streams of information is altered. The components are transferred via a common signal path such that upon transfer, the original time relation between the streams of information may be restored.

System, method, and apparatus for fractional delay

A spreading system according to an embodiment of the invention spreads two data signals. The system produces a filtered signal that is based on one of the data signals and an output signal that is based on both of the data signals. In one example, a spreading system is used to perform QPSK spreading of two data signals, including separate processing of the two data signals, in a practical manner. Such separate control may include filtering and/or gain control.

System for direct sequence spreading

A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.

Digital filter with state storage

Interleavers are used in data transmission and storage applications to introduce diversity into a data stream, thereby making adjacent symbols more independent with respect to a transfer environment of variable quality. Conventional interleavers require storage in whole units of data blocks. This storage requirement complicates implementations for applications where available circuit area is limited and data rates and block sizes are large. A novel interleaver produces an interleaved data block using storage space that is only a fraction of the size of the input data block.

Method and apparatus for interleaving for information transmission or storage applications

A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control

In applications employing phase-shift keying modulation, a phase rotator as disclosed herein is used to rotate the constellation of signal vectors before carrier modulation in order to maximize modulator output power. Such a rotator may be applied in the digital domain (to complex signals having either binary-valued or multi-valued components) or in the analog domain.

Method and apparatus for rotating the phase of a complex signal

A need to store data between a producing stage and a consuming stage commonly arises in digital processing applications. However, factors such as fabrication process limitations and circuit area constraints may restrict the amount of available storage. A novel method and apparatus for data buffering are disclosed which use less data storage than would be required by double buffering techniques.

Method and apparatus for buffering data transmission between producer and consumer

The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.

Variable length instruction decoder

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Deepu John