Texas Instruments Corporation

Deependra Talla

Ching-Yu Hung

Youngjun Yoo

Shinri Inamori

David E Smith

Damon Domke

Clay Dunsmore

A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Scalable multi-threaded sequencing/synchronizing processor architecture

This invention is a programmable image pipe processing architecture that offers full software flexibility to implement latest and greatest algorithms at fully hardwired performance levels. This invention achieves hardwired image pipe processing performance but offers full flexibility and programmability of software achieving the best of both hardwired and software image pipes processing.

Programmable architecture for flexible camera image pipe processing

A digital video acquisition system including a plurality of image processors (A;B) is disclosed. A CCD imager () presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (A) captures and encodes a first group of frames, and instructs a slave image processor (B) to capture and encode a second group of frames presented by the CCD imager () before the encoding of the first group of frames is completed by the master image processor. The master image processor (A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (B) are transferred to the master image processor (A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (A;). The parameters of the encoding operation can be dynamically adjusted, for example in response to the nature of the video sequences being captured.

Video encoding using parallel processors

A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.

Video processing subsystem architecture

A programmable data reformatter reorders output from an image sensor to yield various formats. The reformatting applies to reduced resolution output from large image sensors as in digital cameras operating in video mode, and converts an irregular video mode output to a standard format, such as Bayer pattern, for image processing.

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Plano, TX, United States of America

Deependra Talla