Freescale Semiconductor,inc.

Nxp Usa, Inc.

Nxp B.v.

Deependra Kumar Jain

Krishna Thakur

Gaurav Agrawal

Anand Kumar Sinha

Vinod K Jain

Sanjay Kumar Wadhwa

Saurabh Goyal

Ravi Kumar

Divya Tripathi

Ateet Omer

Ravichandar Reddy Geetla

Devesh P Singh

Avinash Chandra Tripathi

Atul Dahiya

Pawan Sabharwal

Ankesh Jain

Avinish Chandra Tripathi

Raghav Mehta

A low current, adaptively-biased switched resistor digital-to-analog converter (RDAC) circuit, method and apparatus are provided with a coarse trim ladder and a fine trim ladder connected with a plurality of NFET switches to generate an output reference voltage from an input supply voltage, where the bulk semiconductor substrate regions for the NFET switches in at least the fine trim ladder are driven by a unity gain buffer which is connected in feedback to receive the output reference voltage and to generate a buffered reference voltage which is directly connected to bulk semiconductor regions of the NFET switches, thereby providing a low current, low circuit area solution with reduced leakage current and temperature variation.

RDAC ladder with adaptive biasing to reduce the reference variation across temperature

A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.

Digital frequency synthesizer

An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.

System and method for controlling tuning in electronic circuitries

A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.

Multiphase digital frequency synthesizer with fractional division

An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Circuitry and methods for fractional division of high-frequency clock signals

A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

Digital phase-locked loop

An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.

Initialization circuit of delay locked loop

An enabling system that includes a controller and processing circuitry, is configured to enable an external oscillator that operates in one of single-ended, differential, and crystal modes. To enable the external oscillator, the controller is configured to detect a mode of operation of the external oscillator, and the processing circuitry is configured to operate in the detected mode. The controller detects the mode of operation of the external oscillator by sequentially initializing the processing circuitry to operate in the single-ended, differential, and crystal modes, and determining whether the current operating mode of the processing circuitry is same as the mode of operation of the external oscillator based on a clock signal outputted by the processing circuitry during the corresponding mode.

System for enabling external oscillators in system-on-chips

A delay-locked loop (DLL) includes a delay line configured to receive a reference clock signal and a control signal, and generate a first plurality of clock signals. Each clock signal of the first plurality is configured to have a different phase delay relative to the reference clock signal. A phase frequency detector is coupled to the delay circuit and is configured to receive a first clock signal and a second clock signal of the first plurality, and generate up and down control signals. A charge pump is coupled to receive the up and down control signals and generates a charge pump current based on the up and down control signals. An output of the charge pump is coupled to the delay line at a voltage control node. An initialization circuit is coupled to the voltage control node and is configured to generate an initialization voltage based on the reference clock signal frequency.

Delay-locked loop having initialization circuit

A delay-locked loop (DLL) has a fractional phase frequency (PF) detector that reduces false locking and harmonic locking. The PF detector has a trunk, an upper branch, a lower branch, and a logic module. A delay line provides the PF detector a set of fractional phase-delayed clock signals that are used to prime and/or activate corresponding flip-flops of the trunk, upper branch, and lower branch in a sequence. The use of flip-flops in the lower branch activated by different fractional phase-delayed clock signals avoids false locking and harmonic locking over a wider range of initial delay magnitudes than conventional DLLs.

Delay-locked loop circuit with fractional phase frequency detector

A clock generator includes a diagnostic circuit that includes first and second muxes, first and second comparators, a logic gate, and a counter. The first mux receives first and second voltage signals and outputs a first intermediate signal based on a control signal. The second mux receives third and fourth voltage signals and outputs a second intermediate signal based on the control signal. The first and second comparators compare the intermediate signals with a first signal that is indicative of a DC value of the clock signal for generating first and second comparison signals. The logic gate receives the first and second intermediate signals and generates a control signal. The counter receives the clock signal and the control signal and generates a clock ready signal that is indicative of stability and quality of the clock signal.

Clock generator circuit

A buffer circuit includes an inverter and a level-shifter. The inverter receives a first oscillating signal at a first voltage level and generates an inverted version of the first oscillating signal at a second voltage level. The level-shifter receives a second oscillating signal at a third voltage level, which has a phase difference from the first oscillating signal, and the inverted first oscillating signal, and generates a buffer output signal at a fourth voltage level.

Buffer circuit for voltage controlled oscillator

A level shifter circuit for level shifting voltages of signals crossing multiple circuit domains includes an input stage and a driver stage. The input stage receives an oscillating signal generated by a ring oscillator and generates an inverted oscillating signal. The differential oscillating signals are provided to the driver stage, which level shifts a voltage level of the oscillating signal to a level of a supply voltage of the ring oscillator.

Level shifter circuit

A phase locked loop (PLL) system generates an oscillator signal by providing a fixed control voltage to a programmable voltage to current converter having switch selection inputs and a variable current output. Logic values are provided to the switch selection inputs to adjust a control current at the variable current output and a frequency of the oscillator signal is adjusted based on the control current. The logic values are fixed when a first condition is reached, which is based on the frequency of the oscillator signal, a division factor, and an input reference signal frequency. The fixed control voltage provided to the programmable voltage to current converter is then replaced with a charge pump control voltage based on an error signal. The error signal is based on a comparison of the input reference signal frequency and a fraction of the oscillating frequency.

Phase locked loop and method for generating an oscillator signal

A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current. A current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio, based on a second current generated by a current mirror circuit and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents. The active loop filter includes an input capacitance that varies with a variation in the predetermined ratio of the charge pump currents. The active loop filter also includes a transconductance stage having a transconductance that varies based on a third current generated by a current mirror circuit. The PLL bandwidth is independent of PVT variations and dependent only on the frequency of the input reference signal. In addition, the size of the input capacitor is relatively small so that the circuit requires very little space.

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Noida, India

Deependra Kumar Jain