Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sandisk Corporation

Deepanshu Dutta

Huai-Yuan Tseng

Xiang Yang

Jeffrey W Lutze

Yu-Chung Lien

Dengtao Zhao

Muhammad Masuduzzaman

Masaaki Higashitani

Ken Oowada

Jiahui Yuan

Sarath Chandran Puthenthermadam

Ravi J Kumar

Dana Lee

Gerrit Jan Hemink

Yan Li

Zhenming Zhou

Henry Chin

Grishma Shah

Zhiping Zhang

Shih-Chung Lee

Peng Zhang

Chun-Hung Lai

Yingda Dong

Jun Wan

Mohan Dunga

Tai-Yuan Tseng

Shinji Sato

Xue Bai Pitner

Cynthia Hsu

Navneeth Kankani

Idan Alrod

Man Lung Mui

Murong Lang

Wei Zhao

Abhijith Prakash

Hua-Ling Cynthia Hsu

Nan Lu

Arash Hazeghi

Jian Feng Chen

Christopher John Petti

James K Kai

Abhijeet Manohar

Aaron Lee

Niles Yang

Mark Murin

Anubhav Khandelwal

Jiacen Guo

Guirong Liang

Yi Song

Jong Hak Yuh

Wenzhou Chen

Chin-Yi Chen

Yi-Chieh Chen

Amul Dhirajbhai Desai

Fanqi Wu

Eran Sharon

Johann Alsmeier

Sergey Anatolievich Gorobets

Yanli Zhang

Steven Theodore Sprouse

Chris Avila

Seungpil Lee

Koichi Nishimura

Ning Ye

Tien-Chien Kuo

Changyuan Chen

Bo Lei

Deepak Raghu

Mark Shlick

Zhongguang Xu

Mrinal Kochar

Ishai Ilani

Linh Tien Truong

Yuki Mizutani

Farookh Moogat

Jin Liu

Suresh Kumar Upadhyayula

Long C Pham

Ohwon Kwon

Tomer Eliash

Abu Naser Zainuddin

David Rozman

Parth Amin

Alon Eyal

Alex Mak

Kou Tei

Yichao Huang

Wei Cao

Matthias Baenninger

Hiroyuki Mizukoshi

Sujjatul Islam

Yen-Lung Li

Jianzhi Wu

Hideto Tomiie

Huiwen Xu

Toru Ishigaki

Chris Yip

Yew Yin Ng

Sanghyun Lee

Piyush Dak

A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.

Dual-way sensing scheme for better neighboring word-line interference

Technology for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.

Open block read ICC reduction

A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.

Dynamic 1-tier scan for high performance 3D NAND

The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.

High performance verify techniques in a memory device

A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.

Non-volatile memory with erase depth detection and adaptive adjustment to programming

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.

Apparatus and method for detecting neighbor plane erase failures

A storage device is provided that conditionally performs read refresh in blocks having higher P/E cycles or older programming times, while refraining from performing read refreshes in blocks having lower P/E cycles or recent programming times. The storage device includes a memory and a controller. The memory includes a block having cells. The controller performs a read refresh on the cells when a number of P/E cycles of the block exceeds an age threshold or after a threshold amount time has elapsed since data was programmed in the block. The controller may also refrain from performing read refreshes on the cells until the number of P/E cycles exceeds the age threshold or until a threshold amount of time has elapsed since the data is programmed. As a result, lower BER may occur due to wider Vt margins, while power and system overhead may be saved.

Data retention-specific refresh read

An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.

Three-bit-per-cell programming using a four-bit-per-cell programming algorithm

A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

CELSRC voltage separation between SLC and XLC for SLC program average ICC reduction

The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.

Low power read method and a memory device capable thereof

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.

Pump skip for fast single-level cell non-volatile memory

A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.

High speed multi-level cell (MLC) programming in non-volatile memory structures

A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.

Memory apparatus and method of operation using state dependent strobe tier scan to reduce peak ICC

A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N−1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line. Determining the data states, determining the program voltage configuration, and performing the program operation may be repeated until a program stop condition is satisfied.

Neighbor aware multi-bias programming in scaled BICS

A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.

Programming of memory cells using a memory string dependent program voltage

Growing community of inventors

Fremont, CA, United States of America

Deepanshu Dutta