Vlsi Technology, Inc.

Deepak Verma

W Henry Potts

A fully associative cache memory has a finite state machine which creates and maintains a linked list structure within the cache. This linked list structure allows the fully associative cache memory to be implemented in a structure other than a complex FIFO arrangement, as is typically required by systems of the prior art.

Method for providing an improved fully associative cache memory having a

A digital computer system including a memory subsystem thereof for increasing the throughput of the digital computer system is disclosed, comprising a central processing unit (CPU), a main memory, and a Look-ahead Instruction Prefetch Buffer (LIPB) external to the CPU for prefetching at least one portion of instruction code from the main memory each time the CPU initiates a request for instruction code from the main memory and for accelerating the submission of the portion of instruction code to said CPU means upon request by said CPU means without a memory system delay that is usually required when accessing a larger number of memory locations in the main memory each time the CPU initiates an instruction code request. An intelligent posted write buffer (IPWB) is also provided for temporarily storing in a first-in first-out (FIFO) configuration a portion of write-to-memory data generated by the CPU executing a write operation and for subsequently applying the portion of write-to-memory data to the main memory thereby eliminating a possible stall incurred by the CPU while waiting for the write operation to be completed.

Growing community of inventors

Phoenix, AZ, United States of America

Deepak Verma