Seagate Technology Incorporated

Seagate Technologies, Inc.

Deepak Sridhara

Ara Patapoutian

Jason Bellorado

William Michael Radich

Prafulla Bollampalli Reddy

Marcus Marrow

Jason Charles Jury

Arvind Sridharan

Richard Jay Parshall

Bruce Douglas Buch

Zheng Wang

Rishi Ahuja

Ching He

Mark A Gaertner

Timothy Richard Feldman

Barmeshwar Vikramaditya

Ivana Djurdjevic

Raman Venkataramani

Bengt Anders Ulriksson

Belkacem Derras

Jeffrey John Pream

Raman Venkataranmani

Fatih Erden

Kinman Ng

An error recovery process provides for selecting a first recovery scheme for a decoding attempt on a first subset of a set of failed data blocks read from a data track; selecting a second different recovery scheme for a decoding attempt on a second subset of the set of failed data blocks read from the data track; and during a single revolution of the data track, performing operations to decode a first subset of the failed data blocks according to the first recovery scheme operations to decode the second subset of the failed data blocks according to the second different recovery scheme.

Decoding policy management to support multiple decoding schemes in a single buffer space

Systems and methods are disclosed for an improved utilization of parity within a data storage device, and manufacturing methods thereof. In some embodiments, a data storage device can implement an improved codeword redundancy process that can be utilized for data storage locations which were not previously scanned for defects. In some embodiments, a data storage device can implement an improved codeword redundancy process to store write data to a data storage location without having to perform a read operation prior to storing the write data to the storage location. The improved codeword redundancy process can include various methods of storing or updating an outer code codeword for the data to be stored.

Codeword redundancy

A method includes encoding a sector of data to be written to a data storage device with a single error correcting code (ECC). The sector of data is divided into N individually readable and writeable portions, with N&#x2265;2. The individually readable and writeable portions of the sector of data are separated with a space between the portions of the sector of data in a pattern.

Coarse interleaving

In one implementation, the disclosure provides a decoding system that concurrently executes a read sample combining recovery process and an iterative outer code (IOC) recovery process. Performing the read sample combining recovery process entails executing multiple rounds of logic that each provide for combining together different data samples read from a data block. The IOC recovery process is performed at least partially concurrent with the read sample combining recovery process and each round of the IOC recovery process is based on newly-updated data samples generated by the read sample combining recovery process.

Concurrent recursive-read averaging and iterative inner and outer code decoding

Sync-mark (SM) detection recovery techniques for HDDs tend to be slow and cumbersome. Typical approaches often require an entire read command to be aborted and multiple subsequent read commands with significant firmware intervention. Should a data sector be unreadable, an example recovery technique for HDDs is recursive read averaging (RRA). Using RRA, samples for failed sector reads are stored in memory. When a sector is subsequently read, the samples are averaged and replace the prior sample stored in memory. The averaged samples are then used to decode the sector. Should SMs associated with data fragments making up a sector be unreadable, the data fragments are unreadable, rendering the sector unreadable. The systems and methods described herein are used to recover previously unreadable SMs. When updated data fragments are subsequently recombined, the confidence level in the overall sector is improved, which increases the likelihood of a successful decode of the sector.

Sync-mark detection error recovery

A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.

Method and apparatus for LDPC decoding using indexed messages

An error recovery process provides for identifying a set of failed data blocks read from a storage medium during execution of a read command, populating sample buffers in a read channel with data of a first subset of the set of failed data blocks, and initiating an error recovery process on the data in the sample buffers. Responsive to successful recovery of one or more data blocks in the first subset, recovered data is released from the sample buffers and sample buffers locations previously-storing the recovered data are repopulated with data of a second subset of the set of failed data blocks. The error recovery process is then initiated on the data of the second subset of the failed data blocks while the error recovery process is ongoing with respect to data of the first subset of failed data blocks remaining in the sample buffers.

Read channel buffer management for higher throughput decoding

An apparatus may include a circuit configured to initialize a read operation to read one or more requested data segments of a respective data unit having a plurality of data segments. Based on a number of failed data segments of the requested data segments and an erasure capability of an outer code error correction scheme, the circuit may perform erasure recovery to recover the failed data segments. Based on the number of failed data segments, the erasure capability of the outer code error correction scheme, and a threshold value, the circuit may perform iterative outer code recovery to recover the failed data segments.

Efficient read and recovery with outer code

In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

Non-linear LLR look-up tables

Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.

Error correction with multiple LLR-LUTS for a single read

Systems and methods are disclosed for error recovery in a digital data channel. In an error recovery approach when the hardware fails to recover a sector, the sample for that sector can be saved along with a metric measure that indicates the quality of the sample. This process can begin from a first on-the-fly receiving and decoding of data. During each step of error recovery, a retry attempt may either use samples obtained during a new decoding attempt or may use a sample, or a combination of samples, having the best metric from an earlier attempt, or a combination of earlier attempts, to perform the recovery during a current retry recovery attempt.

Selective sampling for data recovery

Systems and methods are disclosed for implementing sector management in drives having multiple modulation coding. A circuit may be configured to generate a data sector having a first number of bits based on a first modulation encoding scheme associated with a first location of a data storage medium, determine a difference between the first number of bits and a second number of bits corresponding to a second modulation encoding scheme associated with a second location of the data storage medium, append a number of padding bits to the data sector based on the difference, and store the data sector to the second location of the data storage medium. The data sector may be a sector reallocated from the first location to the second location. The data sector may also be an intermediate parity sector stored to a media cache region of the data storage device.

Sector management in drives having multiple modulation coding

Systems and methods are disclosed for employing variable amounts of parity sectors. In certain embodiments, an apparatus may comprise a processor configured to generate a first number of parity sectors for write data to be written to a nonvolatile memory, and store the write data and a second number of parity sectors to the nonvolatile memory, the second number of parity sectors being a subset less than all of the first number of parity sectors. The processor may further select additional parity sectors from the first number of parity sectors based on error metrics for the write data, store the additional parity sectors to the nonvolatile memory, and perform error recovery on the write data based on the additional parity sectors.

Variable parity sectors

An apparatus may include a circuit that initializes a read operation to read one or more requested data segments of a respective data unit. The circuit may generate equalized combined samples for a failed data segment of the one or more requested data segments based on first samples and second samples. In addition, the circuit may perform iterative outer code recovery for the data unit utilizing the equalized combined samples as samples for the failed data segment.

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Longmont, CO, United States of America

Deepak Sridhara