Samsung Electronics Co., Ltd.

Deepak Sharma

Chul-hong Park

Raheel Azmat

Sang-jun Park

Hyun-jong Lee

Jae-Seok Yang

Chul Hong Park

Jae Seok Yang

Chulhong Park

Kwan Young Chun

Subhash Kuchanuri

Su-Hyeon Kim

Nitin Kishorbhai Tanwar

Kamya Jaiswal

Pratush Kumar Srivastava

Rajeev Ranjan

Kuchanuri Subhash

Akshar Bhatnagar

Asif Anis

Sushant Vobbilisetty

Rastogi Sidharth

A method for providing sign language is disclosed. The method includes receiving, by an electronic device, a natural language information input from at least one source for conversion into sign language. The natural language information input includes at least one sentence. The method further includes predicting, by the electronic device, an emphasis score for each word of the at least one sentence based on acoustic components. The method further includes rephrasing, by the electronic device, the at least one sentence based on the emphasis score of each of the words. The method further includes converting, by the electronic device, the at least one rephrased sentence into the sign language. The method further includes delivering, by the electronic device, the sign language.

Method and electronic device for providing sign language

Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Integrated circuit and standard cell library

Integrated circuit devices are provided. The IC devices may include an active region extending in a first direction, first and second gate electrodes extending in a second direction, a first impurity region in the active region adjacent a first side of the first gate electrode, a second impurity region in the active region between a second side of the first gate electrode and a first side of the second gate electrode, a third impurity region in the active region adjacent a second side of the second gate electrode, a cross gate contact electrically connecting the first and second impurity regions, a first contact electrically connected to the third impurity region, a first wire electrically connected to the cross gate contact, and a second wire electrically connected to the first contact. The first and second wires may extend only in the first direction and may be on the same line.

Integrated circuit (IC) devices including cross gate contacts

An integrated circuit (IC) device includes at least one standard cell. The at least one standard cell includes: first and second active regions respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction; first and second gate lines extending parallel to each other in a second direction perpendicular to the first direction across the first and second active regions, a first detour interconnection structure configured to electrically connect the first gate line with the second gate line; and a second detour interconnection structure configured to electrically connect the second gate line with the first gate line. The first and second detour interconnection structures include a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via.

Integrated circuit devices

Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

Semiconductor device

Growing community of inventors

Suwon-si, South Korea

Deepak Sharma