Intel Corporation

Deepak Samuel Kirubakaran

Russell Jerome Fenger

Jianfang Olena Zhu

Rajshree Chabukswar

Raoul Rivas Toledano

James G Hermerding, Ii

Chee Lim Nge

Zhongsheng Wang

Jianwei Dai

William A Braun

Eliezer Weissmann

Kristoffer Fleming

Sudheer Nair

Ivan Chen

Udayan Kapaley

Paul S Diefenbaugh

Vishal Ravindra Sinha

Chia-Hung Sophia Kuo

Hisham Abu Salah

Mark J Gallina

Monica Gupta

Vijay Dhanraj

Ashraf H Wadaa

Virendra Vikramsinh Adsure

Renji Thomas

Efraim Rotem

Martin Guy Dixon

Barnes Cooper

Aleksander Magi

Guy M Therien

Asit K Mallick

Michael D Rosenzweig

Premanand Sakarda

Bo Qiu

Srikanth Potluri

Duncan Glendinning

Kathy Bui

Marko Bartscherer

Yifan Li

Hisham Abu-Salah

Marc D Torrant

Jin Yan

Melanie Daniels

Israel Hirsh

Richard R Winterton

Noor Mubeen

Arjan Van De Ven

Adam J Norman

Columbia Mishra

Akhilesh P Rallabandi

Deepak Gandiga Shivakumar

Venkateshan Udhayan

Amir Ali Radjai

Srinivas Pandruvada

Carin Ruiz

Refael Mizrahi

Andrey Gabdulin

Ramakrishnan Sivakumar

Chris Binns

Ahmed Shams

Lingjing Zeng

Sze Ling Yeap

Nicholas Klein

Chad Gutierrez

Houfei Chen

Ryan Thompson

Arthur Leonard Brown

Georgina Saborio Dobles

Lawrence Falkenstein

Arijit Chattopadhyay

Kai P Wang

Jun Pan

Srividya Ambale

Rafal J Wysocki

Taeyoung Kim

James Hermerding Ii

An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.

Methods and apparatus to adapt memory channel usage on a per-user basis

Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.

Methods, systems, and apparatus to reconfigure a computer

Methods and apparatus for bi-directional control of computing unit frequency are disclosed. An example apparatus to control a frequency of a computing unit includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to determine a performance hint from a first register, the performance hint corresponding to a requested performance of the computing unit for executing a thread associated with software, determine power and performance (PnP) statistics pertaining to the thread from a second register, control the frequency of the computing unit based on the performance hint and the PnP statistics, and provide a pressure of the computing unit to the software.

Methods and apparatus for bi-directional control of computing unit frequency

Methods and apparatus to improve user experience on computing devices are disclosed. An example computing device includes an image sensor. The example computing device further includes wireless communication circuitry. The example computing device also includes an operations controller to cause the wireless communication circuitry to switch between different operation modes based on an analysis of image data generated by the image sensor. Different ones of the operation modes to consume different amounts of power.

Methods and apparatus to improve user experience on computing devices

A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

Hardware and software coordinated cost-aware low power state selection

In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

System, apparatus and method for dynamically adjusting platform power and performance based on task characteristics

A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vfor energy-efficiency. Such Vvalues may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest V. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest V. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Energy-efficient core voltage selection apparatus and method

Methods, apparatus, and systems to dynamically schedule a workload to among compute blocks based on temperature are disclosed. An apparatus to schedule a workload to at least one of a plurality of compute blocks based on temperature includes a prediction engine to determine (i) a first predicted temperature of a first compute block of the plurality of compute blocks and (ii) a second predicted temperature of a second compute block of the plurality of compute blocks. The apparatus also includes a selector to select between the first compute block and the second compute block for assignment of the workload. The selection is based on which of the first and second predicted temperatures is lower. The apparatus further includes a workload scheduler to assign the workload to the selected one of the first or second compute blocks.

Methods, apparatus, and systems to dynamically schedule workloads among compute resources based on temperature

Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

Methods and apparatus to manage energy usage and compute performance

Methods and apparatus to manage power and performance of computing devices based on user presence are disclosed. An apparatus includes an engagement detector to determine an engagement of a user with a device based on at least one of image data generated by an image sensor or an application running on the device; and an operation mode selector to select one of a plurality of operation modes for the device based on a level of engagement of the user, the plurality of operation modes including (1) a first operation mode associated with the device operating at a first performance level and a first power level and (2) a second operation mode associated with the device operating at a second performance level and a second power level, the first performance level being higher than the second performance level, the first power level being higher than the second power level.

Methods and apparatus to manage power and performance of computing devices based on user presence

A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.

Technology for dynamically grouping threads for energy efficiency

In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

Utilization metrics for processing engines

Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

Dynamic performance biasing in a processor

Growing community of inventors

Hillsboro, OR, United States of America

Deepak Samuel Kirubakaran