Virage Logic Corporation

Synopsys, Inc.

Deepak Sabharwal

Amit Khanuja

Alexander Shubat

Vineet Kumar Sachan

Subramani Kengeri

Adam Kablanian

Prakash Ravikumar Bhatia

Sanjiv Kainth

Andrew F Knight

Yong Zhang

Alex Shubat

Niranjan Behera

Shreekanth Sampigethaya

Deepak Kumar Mehta

Izak Kense

Raymond Tak-Hoi

A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes generating a logic zero at a source of the transistor by electrically connecting the source of the transistor to a ground line with the first conductor. Further, the method includes, programming the read only memory cell to logic zero. A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes, connecting electrically a source of the transistor to the drain with the first conductor. Further, the method includes programming the read only memory cell to logic one.

Compact read only memory cell

A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.

Low leakage ROM architecture

Read only memory (ROM) with minimum leakage is provided. The ROM includes a read only memory array. The read only memory array includes a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. Another ROM includes a first transistor comprising a gate, electrically connected to a word line to provide a read signal, a drain, electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal. Further, a reference word line is electrically connected to a gate of a fourth transistor.

A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.

Systems and methods for reducing memory array leakage in high capacity memories by selective biasing

A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Compact virtual ground diffusion programmable ROM array architecture, system and method

A Static Random Access Memory (SRAM) cell having a source-biasing mechanism for leakage reduction. In standby mode, the cell's wordline is deselected and a source-biasing potential is provided to the cell. In read mode, the wordline is selected and responsive thereto, the source-biasing potential provided to the cell is deactivated. Upon completion of reading, the source-biasing potential is re-activated.

Source-biased SRAM cell with reduced memory cell leakage

A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array having M rows and N columns. A shared source line is associated with each pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. Likewise, a shared bit line is associated with each pair of adjacent columns, except with respect to the edge columns of the array, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical '0' and logical '1'. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.

Method and system for accelerated detection of weak bits in an SRAM memory device

A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.

Multi-port memory utilizing an array of single-port memory cells

A memory compiler characterization system and method for determining parametric data, wherein memory compilers of a first type are rigorously characterized and memory compilers of a second type are sparsely characterized with respect to a particular parameter. Absolute scale factors are determined based on the ratio of the parametric data points of two congruent memory compilers, one from each type. Interpolated scale factors are obtained based on the absolute scale factors. Parametric data for the remaining compilers of the sparsely characterized compiler set is filled out by applying the interpolated scale factors in conjunction with the data of the congruent memory compilers of the first type.

System and method for memory compiler characterization

A source-biasing mechanism for leakage reduction in SRAM. In standby mode, wordlines are deselected and a source-biasing potential is provided to SRAM cells. In read mode, a selected wordline deactivates the source-biasing potential provided to the selected row of SRAM cells, whereas the remaining SRAM cells on the selected bitline column continue to be source-biased.

Wordline-based source-biasing scheme for reducing memory cell leakage

Methods and apparatuses in which a ROM memory array has virtual-grounded source lines programmed in layer physically higher than the diffusion layer. The ROM memory array may include a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines. At least one of the virtual-grounded source lines is programmed with a layer physically higher than the diffusion layer.

Methods and apparatuses for a ROM memory array having a virtually grounded line

Various methods, apparatuses, and systems in which a read only memory is arrayed in a multiple rows and columns. A first column of memory cells is organized into groups of memory cells including a first group of memory cells and a second group of memory cells. A first source line connects to one or more memory cells in the first group of memory cells. The first source line changes its voltage state during a read operation on one or more bit cells in the first group. A second source line connects to one or more memory cells in the second group of memory cells. The second source line maintains its voltage state during the read operation.

Methods and apparatuses for a ROM memory array having twisted source or bit lines

A memory characterization system and method using a hierarchically-stitched netlist generation technique. A plurality of leaf cells forming a memory instance are generated based on a minimum area required to encompass an optimal number of memory strap points relating to global signals that span the memory instance. Input and output pins are defined for each tile with respect to the global signals in both horizontal and vertical directions. A parametric dataset is obtained for each tile using an extractor (wherein the memory instance is in post-layout condition) or a pre-layout wire-delay estimator. The parametric netlist for the entire memory instance is assembled by coupling the individual parametric datasets using the input and output pins of the tiles with respect to the global signals.

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Fremont, CA, United States of America

Deepak Sabharwal