Sandisk Technologies Inc.

Silicon Laboratories Inc.

Deepak Pancholi

Bhavin Odedara

Manuel Antonio d'Abreu

Stephen L Skala

Radhakrishnan Nair

Dimitris C Pantelakis

Srikanth Bojja

Naidu Prasad

Jayaprakash Naradasi

Srinivasa Rao Sabbineni

Santhosh Kumar

Prasad Naidu

Hasan Ali Stationwala

Ayan Ghosh

Vishal Rustagi

Smitha Naganna

Rohit Reddy

A retry technique reduces or eliminates redundant transmit streams and redundant retransmissions when multiple devices are listening to the same audio stream. The retry techniques reduce power consumption and reduce airtime usage. The retry technique includes communicating data using a hybrid isochronous group including a plurality of broadcast isochronous streams from a source device to a plurality of sink devices. The hybrid isochronous group includes, for each broadcast isochronous stream, a group of connected isochronous streams including a connected isochronous stream to the source device from each of the plurality of sink devices. The broadcast isochronous streams communicate the data and the connected isochronous streams communicate acknowledgements of receiving the data.

Retry mechanism for low energy communications

A buck power converter creates a desired output voltage from a greater input voltage with higher efficiency than linear regulators or charge pumps. For compact-size and cost sensitive products, the use of the buck power converter is hindered mainly because of lack of physical space and increases in the cost of the passive components like the inductor and capacitor. Techniques are presented to reduce the sizes of the passive components so that they can be integrated on-chip or in-package or on board. A signal converter in the buck power converter determines the duty cycle of a switching control signal. The switching control signal would ordinarily have driven a power switching circuit that provides current to the inductor in the buck power converter. The signal converter outputs a modified (multiphase) switching control signal that includes multiple separated on-periods that taken together approximate the duty cycle of the switching control signal while maintaining the same control loop frequency. The multiphase switching signal drives the power switching circuit to provide current to the inductor during each of the multiple separated on-periods so that the output voltage ripple decreases by a factor of the number of phases in the modified switching signal. In this way, if the ripple amplitude is kept same, the sizes of the passive components can be reduced by the factor of the number of phases in the modified switching control signal.

Multiphase low LC buck regulator

A method for calibrating an oscillator in an electronic device and an electronic device configured for calibration are provided. Multiple signals are sent to the electronic device from another electronic device, such as from a host device. With knowledge of the time interval between the multiple signals, the electronic device may calibrate the oscillator in the electronic device. For example, the electronic device may be a USB-compliant electronic device. The USB-compliant electronic device may receive Start of Frame (SoF) signals from a host device, which in one USB implementation is received at 1 mSec intervals. The USB-compliant electronic device may count the output of the oscillator between receipt of different SoF signals in order to determine the frequency of the oscillator at different oscillator settings.

System and method for calibrating capacitor-based oscillators in crystal-less devices

An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.

Smart bridge for memory core

A method and device for calibrating an oscillator and a temperature sensor in an electronic device are provided. A same temperature cycle, which includes at least two distinct temperatures, may be used to obtain data to calibrate both the oscillator and the temperature sensor. One of the distinct temperatures may comprise an ambient temperature, and a second distinct temperature may comprise a heated temperature greater than the ambient temperature. The electronic device (or a calibration device separate from the electronic device) may receive the readings from the oscillator and the temperature sensor at the two distinct temperatures in the same temperature cycle, and may determine an oscillator correction factor and a temperature sensor correction factor.

System and method for process and temperature calibration of capacitor-based oscillators

A controlled start-up circuit mechanism in a linear voltage regulator can handle a higher supply voltage at start-up and limits the voltage seen at the devices to be lower than the maximum allowed operation voltage. The circuit may regulate voltage for operating a device coupled to a host when the host supply exceeds that necessary for device operation. The controlled start-up mechanism handles a sudden ramp up or spike of supply voltage relative to the device's operational voltage.

Controlled start-up of a linear voltage regulator where input supply voltage is higher than device operational voltage

An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of a memory controller.

A capacitor from a Metal-Oxide-Metal ('MoM') process may include a plurality of metal layers arranged with different design structures. The metal layers may be connected with vias. The metal layers may include wires, such as rows and/or fingers that are arranged for maximizing capacitance between adjacent fingers, as well as between fingers of different metal layers. As the spacing of the fingers is increased, the reliability, yield of final product, and ease of manufacturing both increase. The capacitor increases the spacing of wires/fingers while either maintaining or improving the capacitance per unit area.

Metal-oxide-metal capacitor structure

An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.

An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.

An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to the first semiconductor device. The second semiconductor device includes a charge pump, and the 3D memory does not include a charge pump.

An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.

Tuning circuitry may include a controller that is configured to determine a phase difference for a pair of signals generated at different points in a master delay line of a master-slave delay locked loop (DLL) circuit. One of signals of the pair may be communicated through a slave delay line of the master-slave DLL circuit before the phase difference is determined. A programming delay value used to set a phase delay of the slave delay line may be adjusted or tuned based on the phase difference.

Auto-phase synchronization in delay locked loops

An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.

A proposed inrush control circuit may work in the presence of supply noise. A linear regulator in bypass mode may be designed for inrush current control, but may be susceptible to irregularities from increased supply noise. The circuit may include a splitting of the bypass power MOS that are switched on with some delay during the power on to control the initial power-on inrush current.

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Bengaluru, India

Deepak Pancholi