Qualcomm Incorporated

Deepak Mathew

Marc M Hoffman

Ajay Anant Ingle

Jose Fridman

Sundar Rajan Balasubramanian

Srijesh Sudarsanan

Gerald Sweeney

Yurong Sun

Wanshi Chen

Aamod Dinkar Khandekar

Parvathanathan Subrahmanya

Qiang Shen

Mao Zeng

Mariam Motamed

Garret Shih

Hanfang Pan

Robin Lee Brown

Jianming Zhu

Hongfeng Dong

James Lee

Mansi Jain

Seyedmehdi Sadeghzadeh

Michael John Lopez

Marc Murray Hoffman

Garret Webster Shih

An electronic device receives a single instruction to apply a neural network operation to a set of M-bit elements stored in one or more input vector registers to initiate a sequence of computational operations related to a neural network. In response to the single instruction, the electronic device implements the neural network operation on the set of M-bit elements to generate a set of P-bit elements by obtaining the set of M-bit elements from the one or more input vector registers, quantizing each of the set of M-bit elements from M bits to P bits, and packing the set of P-bit elements into an output vector register. P is smaller than M. In some embodiments, the neural network operation is a quantization operation including at least a multiplication with a quantization factor and an addition with a zero point.

Instruction set architecture for neural network quantization and packing

A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.

Permutation instruction

Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity. The UE may then prioritize the channel state processes and/or may transmit one or more non-current reports.

Channel state computation for enhanced carrier aggregation

An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

System and method for piecewise linear approximation

A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).

Dynamic power scaling of digital modems

Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.

Systems and methods of data extraction in a vector processor

A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

Selective coupling of an address line to an element bank of a vector register file

An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

Device and method for computing a channel estimate

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Acton, MA, United States of America

Deepak Mathew