Intel Corporation

Apple Inc.

Deepak Limaye

James D Allen

Daniel Cutter

John P Shen

Brian Robert Mestan

Gideon N Levinsky

Jose Niell

Ryan N Rakvic

Ravishankar Iyer

Blaise B Fanning

Debra Bernstein

Ioannis T Schoinas

Ronald P Hall

Mridul Agarwal

James Edward Phillips

Brett Stanley Feero

Rohit Kumar Gupta

Stephen J Robinson

Ramadass Nagarajan

Shadi T Khasawneh

Michael D Snyder

Kulin N Kothari

An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

Virtual channel support using write table

Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.

Content-addressable memory filtering based on microarchitectural state

A system and method for efficiently forwarding cache misses to another level of the cache hierarchy. Logic in a cache controller receives a first non-cacheable load miss request and stores it in a miss queue. When the logic determines the target address of the first load miss request is within a target address range of an older pending second load miss request stored in the miss queue with an open merge window, the logic merges the two requests into a single merged miss request. Additional requests may be similarly merged. The logic issues the merged miss requests based on determining the merge window has closed. The logic further prevents any other load miss requests, which were not previously merged in the merged miss request before it was issued, from obtaining a copy of data from the returned fill data. Such prevention in a non-coherent memory computing system supports memory ordering.

Managing serial miss requests for load operations in a non-coherent memory system

In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip (SoC). The conflict detection logic includes snoop filter logic to downgrade a first snooped memory request for a first address to an unsnooped memory request when an indicator associated with the first address indicates that the coherent fabric has control of the first address. Other embodiments are described and claimed.

Providing snoop filtering associated with a data buffer

In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Arbitrating memory accesses via a shared memory fabric

Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed.

Dynamic selection of execution stage

A method and system to schedule out of order operations without the requirement to execute compare, ready and pick logic in a single cycle. A lazy out-of-order scheduler splits each scheduling loop into two consecutive cycles. The scheduling loop includes a compare stage, a ready stage and a pick stage. The compare stage and the ready stage are executed in a first of the two consecutive cycles and the pick stage is executed in a second of the two consecutive cycles. By splitting each scheduling loop into two consecutive cycles, selecting the oldest operation by default and checking the readiness of the oldest operation, it relieves the system of timing requirements and avoids the need for power hungry logic. Every execution of an operation does not appear as one extra cycle longer and the lazy out-of-order scheduler retains most of the performance of a full out-of-order scheduler.

Method and system of scheduling out-of-order operations without the requirement to execute compare, ready and pick logic in a single cycle

A processor is to comprise a central processing unit (CPU), an address generation unit (AGU), an index generation unit and a translation look-aside buffer (TLB). The CPU of the processor is to generate signal to retrieve instructions from a memory. The AGU is to generate a final linear address and an initial linear address after receiving at least three input source values. An index generation unit coupled to the AGU is to generate a set-index value using the bits of at least the three input source values or the bits of the initial linear address even before the bits of the initial linear address are adjusted for carry. A TLB is to generate a physical address using the final linear address and an entry indexed by the set-index value.

Indexing a translation lookaside buffer (TLB)

Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Growing community of inventors

Austin, TX, United States of America

Deepak Limaye