Carrier Corporation

Rutgers, the State University of New Jersey

Virage Logic Corporation

Qpf, Inc. (delaware Corporation)

Deepak Kumar Mehta

Andrew F Knight

Deepak Sabharwal

Devu Manikantan Shila

Michael L Bushnell

Menouer Boubekeur

Xinghao Chen

Alan M Davis

Alie El-Din Mady

Younes Hamdaoui

Omar Khan

Raymond Tak-Hoi

John Lawrence

Raghuveer Ausoori

A tracheostomy tube monitor and alerting apparatus includes: (i) a passive humidification device; and (ii) an integrated monitoring assembly fitted in an opening of a rear sidewall of the passive humidification device. The passive humidification device is configured to be connected to a connector of a tracheostomy tube of a patient. Once connected, the monitoring assembly of the apparatus can begin measuring one or more physiological parameters, such as, air flow, oxygen level, carbon dioxide level, pressure, and moisture. The measurements are compared against threshold values that denote blockage or decannulation. When these threshold values are surpassed, an alarm is actuated to alert a caregiver that the patient may be experiencing obstruction or decannulation of the tracheostomy tube.

Tracheostomy tube monitor and alerting apparatus

Methods, systems and computer program products for intrusion detection are provided. Aspects include receiving, by a processor, internet of things (IoT) device data from each of a plurality of IoT devices, wherein the IoT device data comprises operational data and non-operational data associated with each of the plurality of IoT devices. A security model is built for the plurality of IoT devices based at least in part on the IoT device data, wherein the security model comprises one or more IoT device data ranges. The plurality of IoT devices are monitored to identify a potential intrusion in any of the plurality of IoT devices based at least in part on the IoT device data exceeding any of the one or more IoT device data ranges.

Cyber security framework for internet-connected embedded devices

Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.

Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability

A memory compiler characterization system and method for determining parametric data, wherein memory compilers of a first type are rigorously characterized and memory compilers of a second type are sparsely characterized with respect to a particular parameter. Absolute scale factors are determined based on the ratio of the parametric data points of two congruent memory compilers, one from each type. Interpolated scale factors are obtained based on the absolute scale factors. Parametric data for the remaining compilers of the sparsely characterized compiler set is filled out by applying the interpolated scale factors in conjunction with the data of the congruent memory compilers of the first type.

System and method for memory compiler characterization

Polyester-containing multilayer biaxially-oriented polypropylene films are provided. According to the invention, a two- or three-layer polyester-containing cap layer is bonded to a monoaxially oriented polypropylene core, followed by orientation of the resulting composite in a direction transverse to the direction of orientation of the core layer. At least one tie layer is interposed between the core and the polyester. Advantageously, the polyester contains silicone fluid as a processing aid.

Polyester-containing biaxially-oriented polypropylene films and method

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Sugar Land, TX, United States of America

Deepak Kumar Mehta